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Searched refs:SAR_DPSLP_CTRL (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_pass_v2.h100 __IOM uint32_t SAR_DPSLP_CTRL[2]; /*!< 0x00000030 Deepsleep control for SARv3 */ member
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h1127 #define PASS_SAR_DPSLP_CTRL(sarBase) (((PASS_V2_Type*) cy_device->passBase)->SAR_DPSLP_CTRL[…
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1773 #define PASS_SAR_DPSLP_CTRL(sarBase) (((PASS_V2_Type*) cy_device->passBase)->SAR_DPSLP_CTRL[…