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Searched refs:CY_TDM_SEL_SRSS_CLK0 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_tdm.h268 CY_TDM_SEL_SRSS_CLK0 = 0U, /**< Interface clock is selected as clk_if_srss[0]. */ enumerator
/hal_infineon-3.6.0/mtb-hal-cat1/source/
Dcyhal_audio_common.c1790 pdl_config->tx_config->clkSel = mclk_tx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()
1809 pdl_config->rx_config->clkSel = mclk_rx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()