Searched refs:CY_TDM_SEL_MCLK_IN (Results 1 – 2 of 2) sorted by relevance
984 …bool all_mclk = ((false == cfg->config->rx_config->enable) || (CY_TDM_SEL_MCLK_IN == cfg->config->… in _cyhal_audioss_init_cfg()985 …&& ((false == cfg->config->tx_config->enable) || (CY_TDM_SEL_MCLK_IN == cfg->config->tx_config->cl… in _cyhal_audioss_init_cfg()1790 pdl_config->tx_config->clkSel = mclk_tx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()1809 pdl_config->rx_config->clkSel = mclk_rx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()
272 CY_TDM_SEL_MCLK_IN = 4U /**< Interface clock is selected as tdm_tx/rx_mclk_in. */ enumerator
