Home
last modified time | relevance | path

Searched refs:CY_REG32_CLR_SET (Results 1 – 25 of 31) sorted by relevance

12

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_wdt_b.c223 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_LOWER_ACTION, action); in Cy_WDT_SetLowerAction()
241 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_UPPER_ACTION, action); in Cy_WDT_SetUpperAction()
259 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_WARN_ACTION, action); in Cy_WDT_SetWarnAction()
278 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_AUTO_SERVICE, enable); in Cy_WDT_SetAutoService()
296 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_DPSLP_PAUSE, enable); in Cy_WDT_SetDeepSleepPause()
314 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_HIB_PAUSE, enable); in Cy_WDT_SetHibernatePause()
332 CY_REG32_CLR_SET(SRSS_WDT_CONFIG, WDT_CONFIG_DEBUG_RUN, enable); in Cy_WDT_SetDebugRun()
Dcy_sysclk.c51 CY_REG32_CLR_SET(PERI_DIV_8_CTL[dividerNum], PERI_DIV_8_CTL_INT8_DIV, dividerValue); in Cy_SysClk_PeriphSetDivider()
60 CY_REG32_CLR_SET(PERI_DIV_16_CTL[dividerNum], PERI_DIV_16_CTL_INT16_DIV, dividerValue); in Cy_SysClk_PeriphSetDivider()
102 … CY_REG32_CLR_SET(PERI_DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_INT16_DIV, dividerIntValue); in Cy_SysClk_PeriphSetFracDivider()
103 … CY_REG32_CLR_SET(PERI_DIV_16_5_CTL[dividerNum], PERI_DIV_16_5_CTL_FRAC5_DIV, dividerFracValue); in Cy_SysClk_PeriphSetFracDivider()
113 … CY_REG32_CLR_SET(PERI_DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_INT24_DIV, dividerIntValue); in Cy_SysClk_PeriphSetFracDivider()
114 … CY_REG32_CLR_SET(PERI_DIV_24_5_CTL[dividerNum], PERI_DIV_24_5_CTL_FRAC5_DIV, dividerFracValue); in Cy_SysClk_PeriphSetFracDivider()
304 CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, divider); in Cy_SysClk_ClkSlowSetDivider()
328 CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source); in Cy_SysClk_ClkPumpSetSource()
352 CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider); in Cy_SysClk_ClkPumpSetDivider()
425 CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_CLK_SEL, source); in Cy_SysClk_ClkBakSetSource()
[all …]
Dcy_syspm_v4.c989 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, voltage); in Cy_SysPm_CoreBuckSetVoltage()
1004 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_MODE, mode); in Cy_SysPm_CoreBuckSetMode()
1017 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_VSEL, voltage); in Cy_SysPm_CoreBuckDpslpSetVoltage()
1032 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_MODE, mode); in Cy_SysPm_CoreBuckDpslpSetMode()
1043 …CY_REG32_CLR_SET(SRSS_PWR_CBUCK_DPSLP_CTL, SRSS_PWR_CBUCK_DPSLP_CTL_CBUCK_DPSLP_OVERRIDE, ((enable… in Cy_SysPm_CoreBuckDpslpEnableOverride()
1056 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS_PWR_CBUCK_CTL2_CBUCK_PROFILE, profile); in Cy_SysPm_CoreBuckSetProfile()
1110 … CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_LVL, retLdoParam->activeVoltSel); in Cy_SysPm_RetLdoConfigure()
1111 CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_GAIN, retLdoParam->activeGain); in Cy_SysPm_RetLdoConfigure()
1113 …CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_LVL_DPSLP, retLdoParam->deepsleep… in Cy_SysPm_RetLdoConfigure()
1114 …CY_REG32_CLR_SET(SRSS_PWR_RETLDO_CTL, SRSS_PWR_RETLDO_CTL_RETLDO_GAIN_DPSLP, retLdoParam->deepslee… in Cy_SysPm_RetLdoConfigure()
[all …]
Dcy_sysclk_v2.c57 …CY_REG32_CLR_SET(PERI_DIV_8_CTL(instNum, grpNum, dividerNum), PERI_DIV_8_CTL_INT8_DIV, dividerValu… in Cy_SysClk_PeriPclkSetDivider()
66 …CY_REG32_CLR_SET(PERI_DIV_16_CTL(instNum, grpNum, dividerNum), PERI_DIV_16_CTL_INT16_DIV, dividerV… in Cy_SysClk_PeriPclkSetDivider()
118 …CY_REG32_CLR_SET(PERI_DIV_16_5_CTL(instNum, grpNum, dividerNum), PERI_DIV_16_5_CTL_INT16_DIV, divi… in Cy_SysClk_PeriPclkSetFracDivider()
119 …CY_REG32_CLR_SET(PERI_DIV_16_5_CTL(instNum, grpNum, dividerNum), PERI_DIV_16_5_CTL_FRAC5_DIV, divi… in Cy_SysClk_PeriPclkSetFracDivider()
129 …CY_REG32_CLR_SET(PERI_DIV_24_5_CTL(instNum, grpNum, dividerNum), PERI_DIV_24_5_CTL_INT24_DIV, divi… in Cy_SysClk_PeriPclkSetFracDivider()
130 …CY_REG32_CLR_SET(PERI_DIV_24_5_CTL(instNum, grpNum, dividerNum), PERI_DIV_24_5_CTL_FRAC5_DIV, divi… in Cy_SysClk_PeriPclkSetFracDivider()
439 CY_REG32_CLR_SET(CPUSS_SLOW_CLOCK_CTL, CPUSS_SLOW_CLOCK_CTL_INT_DIV, divider); in Cy_SysClk_ClkSlowSetDivider()
468 CY_REG32_CLR_SET(CPUSS_MEM_CLOCK_CTL, CPUSS_MEM_CLOCK_CTL_INT_DIV, divider); in Cy_SysClk_ClkMemSetDivider()
487 CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source); in Cy_SysClk_ClkPumpSetSource()
498 CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider); in Cy_SysClk_ClkPumpSetDivider()
[all …]
Dcy_scb_uart.c93 CY_REG32_CLR_SET(SCB_CTRL(base), SCB_CTRL_OVS, ovs); in Cy_SCB_UART_SetOverSample()
123 CY_REG32_CLR_SET(SCB_RX_CTRL(base), SCB_RX_CTRL_DATA_WIDTH, (dataWidth - 1UL)); in Cy_SCB_UART_SetDataWidth()
125 CY_REG32_CLR_SET(SCB_TX_CTRL(base), SCB_TX_CTRL_DATA_WIDTH, (dataWidth - 1UL)); in Cy_SCB_UART_SetDataWidth()
151 CY_REG32_CLR_SET(SCB_UART_RX_CTRL(base), CY_SCB_UART_RX_CTRL_SET_PARITY, (uint32_t) parity); in Cy_SCB_UART_SetParity()
154 CY_REG32_CLR_SET(SCB_UART_TX_CTRL(base), CY_SCB_UART_TX_CTRL_SET_PARITY, (uint32_t) parity); in Cy_SCB_UART_SetParity()
180 … CY_REG32_CLR_SET(SCB_UART_RX_CTRL(base), SCB_UART_RX_CTRL_STOP_BITS, ((uint32_t) stopBits) - 1UL); in Cy_SCB_UART_SetStopBits()
183 … CY_REG32_CLR_SET(SCB_UART_TX_CTRL(base), SCB_UART_TX_CTRL_STOP_BITS, ((uint32_t) stopBits) - 1UL); in Cy_SCB_UART_SetStopBits()
208 …CY_REG32_CLR_SET(SCB_UART_RX_CTRL(base), SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR, dropOnParityError); in Cy_SCB_UART_SetDropOnParityError()
233 CY_REG32_CLR_SET(SCB_RX_CTRL(base), SCB_RX_CTRL_MSB_FIRST, enableMsbFirst); in Cy_SCB_UART_SetEnableMsbFirst()
236 CY_REG32_CLR_SET(SCB_TX_CTRL(base), SCB_TX_CTRL_MSB_FIRST, enableMsbFirst); in Cy_SCB_UART_SetEnableMsbFirst()
[all …]
Dcy_syspm_v2.c1104 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_VSEL, voltage); in Cy_SysPm_CoreBuckSetVoltage()
1107 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS, 1UL); in Cy_SysPm_CoreBuckSetVoltage()
1122 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL, SRSS_PWR_CBUCK_CTL_CBUCK_MODE, mode); in Cy_SysPm_CoreBuckSetMode()
1135 CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL3, SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL, inrushLimit); in Cy_SysPm_CoreBuckSetInrushLimit()
1273 CY_REG32_CLR_SET(SRSS_PWR_SDR0_CTL, SRSS_PWR_SDR0_CTL_SDR0_VSEL, voltage); in Cy_SysPm_SdrSetVoltage()
1278 CY_REG32_CLR_SET(SRSS_PWR_SDR0_CTL, SRSS_PWR_SDR0_CTL_SDR0_VSEL, voltage); in Cy_SysPm_SdrSetVoltage()
1291 CY_REG32_CLR_SET(SRSS_PWR_SDR1_CTL, SRSS_PWR_SDR1_CTL_SDR1_VSEL, voltage); in Cy_SysPm_SdrSetVoltage()
1320 CY_REG32_CLR_SET(SRSS_PWR_SDR1_CTL, SRSS_PWR_SDR1_CTL_SDR1_ENABLE, ((enable) ? 1UL : 0UL)); in Cy_SysPm_SdrEnable()
1348 … CY_REG32_CLR_SET(SRSS_PWR_HVLDO0_CTL, SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE, ((enable) ? 1UL : 0UL)); in Cy_SysPm_HvLdoEnable()
1360 CY_REG32_CLR_SET(SRSS_PWR_HVLDO0_CTL, SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL, voltage); in Cy_SysPm_HvLdoSetVoltage()
Dcy_adcmic.c106 CY_REG32_CLR_SET(base->AUXADC_CTRL, MXS40ADCMIC_AUXADC_CTRL_DFMODE, mode); in Cy_ADCMic_Init()
311 …CY_REG32_CLR_SET(base->ADC_MIC_BIAS_PGA_CTRL, MXS40ADCMIC_ADC_MIC_BIAS_PGA_CTRL_MIC_PGA_GAIN_CTRL,… in Cy_ADCMic_SetPgaGain()
364 CY_REG32_CLR_SET(base->AUXADC_CTRL, MXS40ADCMIC_AUXADC_CTRL_DFMODE, locDfMode); in Cy_ADCMic_SetSampleRate()
389 CY_REG32_CLR_SET(base->ADC_GPIO_CTRL, MXS40ADCMIC_ADC_GPIO_CTRL_ADC_DCIN_MUX, channel); in Cy_ADCMic_SelectDcChannel()
Dcy_pdm_pcm.c154 CY_REG32_CLR_SET(PDM_PCM_CTL(base), PDM_CTL_PGA_L, ((uint32_t) gain)); in Cy_PDM_PCM_SetGain()
158 CY_REG32_CLR_SET(PDM_PCM_CTL(base), PDM_CTL_PGA_R, ((uint32_t) gain)); in Cy_PDM_PCM_SetGain()
Dcy_syspm_v3.c1651 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_MODE, mode); in Cy_SysPm_ReghcSelectMode()
1662 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT, drvOut); in Cy_SysPm_ReghcSelectDriveOut()
1673 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_VADJ, trim); in Cy_SysPm_ReghcAdjustOutputVoltage()
1729 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL, SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT, waitTime); in Cy_SysPm_ReghcSetPmicStatusWaitTime()
1759 CY_REG32_CLR_SET(SRSS_PWR_REGHC_CTL2, SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT, timeout); in Cy_SysPm_ReghcEnablePmicStatusTimeout()
Dcy_sar.c159 …CY_REG32_CLR_SET(PASS_ANA_PWR_CFG(base), PASS_V2_ANA_PWR_CFG_PWR_UP_DELAY, trigConfig->pwrUpDelay); in Cy_SAR_CommonInit()
981 CY_REG32_CLR_SET(SAR_RANGE_THRES(base), SAR_RANGE_THRES_RANGE_LOW, lowLimit); in Cy_SAR_SetLowLimit()
1011 CY_REG32_CLR_SET(SAR_RANGE_THRES(base), SAR_RANGE_THRES_RANGE_HIGH, highLimit); in Cy_SAR_SetHighLimit()
Dcy_pra.c2962 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_PRA_ClkDSBeforeTransition()
2972 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_PRA_ClkDSBeforeTransition()
2983 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_IN… in Cy_PRA_ClkDSBeforeTransition()
3054 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_PRA_ClkDSAfterTransition()
3060 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_PRA_ClkDSAfterTransition()
3064 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_PRA_ClkDSAfterTransition()
3085 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_OU… in Cy_PRA_ClkDSAfterTransition()
Dcy_scb_ezi2c.c558 CY_REG32_CLR_SET(SCB_RX_MATCH(base), SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL))); in Cy_SCB_EZI2C_SetAddress1()
1308 CY_REG32_CLR_SET(SCB_RX_MATCH(base), SCB_RX_MATCH_MASK, ((uint32_t) addrMask << 1UL)); in UpdateAddressMask()
Dcy_dmac.c470 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DESCR_TYPE, descriptorType); in Cy_DMAC_Descriptor_SetDescriptorType()
Dcy_dma.c441 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TYPE, descriptorType); in Cy_DMA_Descriptor_SetDescriptorType()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_dmac.h743 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_INTR_TYPE, interruptType); in Cy_DMAC_Descriptor_SetInterruptType()
789 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, triggerInType); in Cy_DMAC_Descriptor_SetTriggerInType()
835 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, triggerOutType); in Cy_DMAC_Descriptor_SetTriggerOutType()
881 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DATA_SIZE, dataSize); in Cy_DMAC_Descriptor_SetDataSize()
926 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE, srcTransferSize); in Cy_DMAC_Descriptor_SetSrcTransferSize()
972 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE, dstTransferSize); in Cy_DMAC_Descriptor_SetDstTransferSize()
1020 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT, retrigger); in Cy_DMAC_Descriptor_SetRetrigger()
1089 CY_REG32_CLR_SET(descriptor->ctl, DMAC_CH_V2_DESCR_CTL_CH_DISABLE, channelState); in Cy_DMAC_Descriptor_SetChannelState()
1137 CY_REG32_CLR_SET(descriptor->xIncr, DMAC_CH_V2_DESCR_X_INCR_SRC_X, srcXincrement); in Cy_DMAC_Descriptor_SetXloopSrcIncrement()
1188 CY_REG32_CLR_SET(descriptor->xIncr, DMAC_CH_V2_DESCR_X_INCR_DST_X, dstXincrement); in Cy_DMAC_Descriptor_SetXloopDstIncrement()
[all …]
Dcy_dma.h833 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType); in Cy_DMA_Descriptor_SetInterruptType()
879 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType); in Cy_DMA_Descriptor_SetTriggerInType()
925 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType); in Cy_DMA_Descriptor_SetTriggerOutType()
971 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize); in Cy_DMA_Descriptor_SetDataSize()
1017 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_SRC_SIZE, srcTransferSize); in Cy_DMA_Descriptor_SetSrcTransferSize()
1063 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize); in Cy_DMA_Descriptor_SetDstTransferSize()
1111 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger); in Cy_DMA_Descriptor_SetRetrigger()
1180 CY_REG32_CLR_SET(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState); in Cy_DMA_Descriptor_SetChannelState()
1228 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_COUNT, xCount - 1UL); in Cy_DMA_Descriptor_SetXloopDataCount()
1279 CY_REG32_CLR_SET(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement); in Cy_DMA_Descriptor_SetXloopSrcIncrement()
[all …]
Dcy_crypto_core_trng.h745 … CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_CTL(base), CRYPTO_TR_MON_CTL_BITSTREAM_SEL, bitStreamSelector); in Cy_Crypto_Core_Trng_MonSetBSSelector()
781 CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_CMD(base), CRYPTO_TR_MON_CMD_START_AP, 1U); in Cy_Crypto_Core_Trng_MonEnableApTest()
796 CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_CMD(base), CRYPTO_TR_MON_CMD_START_AP, 0U); in Cy_Crypto_Core_Trng_MonDisableApTest()
811 CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_CMD(base), CRYPTO_TR_MON_CMD_START_RC, 1U); in Cy_Crypto_Core_Trng_MonEnableRcTest()
826 CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_CMD(base), CRYPTO_TR_MON_CMD_START_RC, 0U); in Cy_Crypto_Core_Trng_MonDisableRcTest()
880 CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_AP_CTL(base), CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16, ccCount); in Cy_Crypto_Core_Trng_MonSetApCC16()
916 CY_REG32_CLR_SET(REG_CRYPTO_TR_MON_AP_CTL(base), CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE, windowSize); in Cy_Crypto_Core_Trng_MonSetApWinSize()
Dcy_cryptolite_trng.h1052 …CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_CTL(base), CRYPTOLITE_TRNG_MON_CTL_BITSTREAM_SEL, bitStre… in Cy_Cryptolite_Trng_MonSetBSSelector()
1088 CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_CTL(base), CRYPTOLITE_TRNG_MON_CTL_AP, 1U); in Cy_Cryptolite_Trng_MonEnableApTest()
1103 CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_CTL(base), CRYPTOLITE_TRNG_MON_CTL_AP, 0U); in Cy_Cryptolite_Trng_MonDisableApTest()
1118 CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_CTL(base), CRYPTOLITE_TRNG_MON_CTL_RC, 1U); in Cy_Cryptolite_Trng_MonEnableRcTest()
1133 CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_CTL(base), CRYPTOLITE_TRNG_MON_CTL_RC, 0U); in Cy_Cryptolite_Trng_MonDisableRcTest()
1187 …CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_AP_CTL(base), CRYPTOLITE_TRNG_MON_AP_CTL_CUTOFF_COUNT16, … in Cy_Cryptolite_Trng_MonSetApCC16()
1223 …CY_REG32_CLR_SET(REG_CRYPTOLITE_TRNG_MON_AP_CTL(base), CRYPTOLITE_TRNG_MON_AP_CTL_WINDOW_SIZE, win… in Cy_Cryptolite_Trng_MonSetApWinSize()
Dcy_scb_i2c.h1189 CY_REG32_CLR_SET(SCB_RX_MATCH(base), SCB_RX_MATCH_ADDR, ((uint32_t)((uint32_t) addr << 1UL))); in Cy_SCB_I2C_SlaveSetAddress()
1235 CY_REG32_CLR_SET(SCB_RX_MATCH(base), SCB_RX_MATCH_MASK, ((uint32_t) addrMask)); in Cy_SCB_I2C_SlaveSetAddressMask()
1284 CY_REG32_CLR_SET(SCB_I2C_CTRL(base), SCB_I2C_CTRL_LOW_PHASE_OVS, (clockCycles - 1UL)); in Cy_SCB_I2C_MasterSetLowPhaseDutyCycle()
1313 CY_REG32_CLR_SET(SCB_I2C_CTRL(base), SCB_I2C_CTRL_HIGH_PHASE_OVS, (clockCycles - 1UL)); in Cy_SCB_I2C_MasterSetHighPhaseDutyCycle()
Dcy_ctb.h1504 … CY_REG32_CLR_SET(PASS_CTBM_CLOCK_SEL(CTBM0), PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL, pumpClk); in Cy_CTB_SetPumpClkSource()
1513 …CY_REG32_CLR_SET(PASS_AREF_AREF_CTRL, PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL, (CY_CTB_CLK_PUMP_PE… in Cy_CTB_SetPumpClkSource()
1526 …CY_REG32_CLR_SET(PASS_AREF_AREF_CTRL, PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL, (CY_CTB_CLK_PUMP_PE… in Cy_CTB_SetClkPumpSource()
Dcy_adcmic.h732 … CY_REG32_CLR_SET(base->AUXADC_CTRL, MXS40ADCMIC_AUXADC_CTRL_BIQUAD_BYPASS, (bypass) ? 1UL : 0UL); in Cy_ADCMic_BiquadBypass()
896 …CY_REG32_CLR_SET(base->ADCMIC_TRIG_INTRPT_TIMER_CTRL, MXS40ADCMIC_ADCMIC_TRIG_INTRPT_TIMER_CTRL_TI… in Cy_ADCMic_SetTimerPeriod()
Dcy_scb_common.h880 CY_REG32_CLR_SET(SCB_RX_FIFO_CTRL(base), SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level); in Cy_SCB_SetRxFifoLevel()
984 CY_REG32_CLR_SET(SCB_TX_FIFO_CTRL(base), SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level); in Cy_SCB_SetTxFifoLevel()
Dcy_syspm.h2031 #define CY_SYSPM_CORE_BUCK_PAUSE_ENABLE(enable) CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, SRSS…
2035 #define CY_SYSPM_CORE_BUCK_OVERRRIDE_ENABLE(enable) CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CTL2, …
2039 #define CY_SYSPM_CORE_BUCK_COPY_SETTINGS_ENABLE(enable) CY_REG32_CLR_SET(SRSS_PWR_CBUCK_CT…
/hal_infineon-3.6.0/core-lib/include/
Dcy_utils.h312 #define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) macro
/hal_infineon-3.6.0/core-lib/
DREADME.md30 …* `CY_REG32_CLR_SET`: Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write operations w…

12