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Searched refs:pll0OutputDiv (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/include/
Dcy_pra_cfg.h233 …uint8_t pll0OutputDiv; /**< PLL0 CLK_PLL_CONFIG register, OUTPUT_DIV … member
/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c2482 pllOutputDiv = devConfig->pll0OutputDiv; in Cy_PRA_CalculatePLLOutFreq()
2857 .outputDiv = devConfig->pll0OutputDiv, in Cy_PRA_SystemConfig()
Dcy_pra.c2272 …structCpy.pll0OutputDiv = ((cy_stc_pra_clk_pll_manconfigure_t *) message->praData1)->praConfig->ou… in Cy_PRA_ProcessCmd()