Searched refs:clock_divider (Results 1 – 5 of 5) sorted by relevance
140 uint32_t clock_divider; in XMC_USIC_CH_SetBaudrate() local160 for(clock_divider = 1023U; clock_divider > 0U; --clock_divider) in XMC_USIC_CH_SetBaudrate()162 pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling)); in XMC_USIC_CH_SetBaudrate()170 clock_divider_min = clock_divider; in XMC_USIC_CH_SetBaudrate()
208 …("XMC_SDMMC_Init: Invalid clock divider value", XMC_SDMMC_CHECK_SDCLK_FREQ(config->clock_divider)); in XMC_SDMMC_Init()215 …sdmmc->CLOCK_CTRL |= (uint16_t)((uint32_t)config->clock_divider << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL… in XMC_SDMMC_Init()
236 …channel->MODCFG = ((uint32_t)config->clock_divider << DSD_CH_MODCFG_DIVM_Pos) | (uint32_t)DSD_CH_M… in XMC_DSD_CH_MainFilter_Init()
415 uint32_t clock_divider: 4; /**< This parameter can take a value of XMC_DSD_CH_CLK_t */ member
628 XMC_SDMMC_SDCLK_FREQ_SEL_t clock_divider; /**< SDMMC clock divider */ member
