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Searched refs:clkSlowDiv (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/include/
Dcy_pra_cfg.h259 …uint8_t clkSlowDiv; /**< Slow clock divider. User has to pass actu… member
/hal_infineon-3.4.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c2233 freq = freq / (devConfig->clkSlowDiv+1UL); /* Output CLK_SLOW frequency */ in Cy_PRA_ValidateClkSlow()
2692 Cy_SysClk_ClkSlowSetDivider(devConfig->clkSlowDiv); in Cy_PRA_SystemConfig()
Dcy_pra.c2353 clkSlowDivTmp = structCpy.clkSlowDiv; in Cy_PRA_ProcessCmd()
2355 structCpy.clkSlowDiv = (uint8_t)(message->praData1); in Cy_PRA_ProcessCmd()
2362 structCpy.clkSlowDiv = clkSlowDivTmp; in Cy_PRA_ProcessCmd()