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Searched refs:SCU_PLL_PLLSTAT_K2RDY_Msk (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.4.0/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c642 while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) in SystemCoreClockSetup()
653 while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) in SystemCoreClockSetup()
664 while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) in SystemCoreClockSetup()
675 while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) in SystemCoreClockSetup()
686 while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) in SystemCoreClockSetup()
/hal_infineon-3.4.0/XMCLib/devices/XMC4500/Include/
DXMC4500.h5268 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY… macro
/hal_infineon-3.4.0/XMCLib/devices/XMC4700/Include/
DXMC4700.h5603 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY… macro
/hal_infineon-3.4.0/XMCLib/devices/XMC4800/Include/
DXMC4800.h5835 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY… macro