Home
last modified time | relevance | path

Searched refs:XTOS_SET_INTLEVEL (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-latest/components/xtensa/include/xtensa/
Dxtruntime.h80 # define XTOS_SET_INTLEVEL(intlevel) 0 macro
91 # define XTOS_SET_INTLEVEL(intlevel) __extension__({ unsigned __tmp; \ macro
113 # define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) macro
138 #define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
140 #define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
143 #define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
147 #define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
152 #define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
/hal_espressif-latest/components/esp_hw_support/include/
Dspinlock.h75 irq_status = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); in spinlock_acquire()
157 irq_status = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); in spinlock_release()
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_cache_esp32s2_esp32s3.c124 irq_status = XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);//mask all interrupts in Cache_WriteBack_Addr()
140 irq_status = XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);//mask all interrupts in Cache_WriteBack_Addr()
/hal_espressif-latest/components/bt/controller/esp32/
Dhli_api.c103 return XTOS_SET_INTLEVEL(XCHAL_DEBUGLEVEL - 2); in hli_intr_disable()
/hal_espressif-latest/components/esp_pm/
Dpm_impl.c486 uint32_t irq_status = XTOS_SET_INTLEVEL(XCHAL_DEBUGLEVEL - 2); in update_ccompare()