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Searched refs:MEMCTL_DCWU_CLR_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_espressif-latest/components/xtensa/include/xtensa/
Dcorebits.h187 #define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK) macro
190 #define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
Dcacheasm.h949 movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12