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Searched refs:EXTMEM_DCACHE_CTRL1_REG (Results 1 – 2 of 2) sorted by relevance

/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dcache_ll.h124 REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_enable_bus()
148 uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG); in cache_ll_l1_get_enabled_bus()
185 REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask); in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dextmem_reg.h44 #define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) macro