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Searched refs:DR_REG_RTCCNTL_BASE (Results 1 – 13 of 13) sorted by relevance

/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h32 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
137 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4)
145 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8)
159 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC)
185 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10)
193 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14)
201 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18)
245 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C)
277 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20)
285 #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x24)
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Dreg_base.h23 #define DR_REG_RTCCNTL_BASE 0x60008000 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h32 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000)
174 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004)
182 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008)
196 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C)
222 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010)
230 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014)
238 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018)
282 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C)
316 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020)
324 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024)
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Dreg_base.h26 #define DR_REG_RTCCNTL_BASE 0x60008000 macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h23 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
207 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4)
215 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8)
229 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc)
243 #define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10)
251 #define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14)
259 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18)
315 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c)
349 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20)
364 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24)
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Dsoc_ulp.h33 REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
37 …REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value)…
Dreg_base.h21 #define DR_REG_RTCCNTL_BASE 0x3ff48000 macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h29 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000)
165 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004)
173 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008)
187 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C)
213 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010)
221 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014)
229 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018)
273 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C)
305 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020)
320 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024)
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Dsoc_ulp.h33 REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
37 …REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value)…
Dreg_base.h31 #define DR_REG_RTCCNTL_BASE 0x3f408000 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h22 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
158 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4)
166 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8)
180 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC)
206 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10)
214 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14)
222 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18)
266 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C)
298 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20)
313 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24)
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Dsoc_ulp.h33 REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
37 …REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value)…
Dreg_base.h14 #define DR_REG_RTCCNTL_BASE 0x60008000 macro