Searched refs:DR_REG_MCPWM_BASE (Results 1 – 6 of 6) sorted by relevance
14 #define DR_REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000)) macro19 #define MCPWM_CLK_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x0)31 #define MCPWM_TIMER0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4)59 #define MCPWM_TIMER0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8)82 #define MCPWM_TIMER0_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc)124 #define MCPWM_TIMER0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10)143 #define MCPWM_TIMER1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x14)171 #define MCPWM_TIMER1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x18)194 #define MCPWM_TIMER1_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x1c)236 #define MCPWM_TIMER1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x20)[all …]
17 #define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)29 #define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)56 #define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)79 #define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)121 #define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)140 #define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)167 #define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)190 #define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)232 #define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)251 #define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)[all …]
26 #define DR_REG_MCPWM_BASE 0x60014000 macro
32 #define DR_REG_MCPWM_BASE 0x60014000 macro
28 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only on…
