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Searched refs:DR_REG_LPPERI_BASE (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dlpperi_reg.h17 #define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
45 #define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
106 #define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
174 #define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8)
190 #define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0xc))
204 #define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x10))
218 #define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x14))
246 #define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x18))
260 #define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x1c))
274 #define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + LPPERI_REG_OFFSET(0x20))
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Dreg_base.h41 #define DR_REG_LPPERI_BASE 0x600B2800 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dlpperi_reg.h17 #define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
78 #define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
139 #define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
151 #define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
163 #define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
189 #define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
201 #define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
213 #define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
253 #define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
266 #define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
Dreg_base.h70 #define DR_REG_LPPERI_BASE 0x600B2800 macro