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Searched refs:core0_status (Results 1 – 1 of 1) sorted by relevance

/hal_espressif-3.6.0/components/esp_system/port/arch/riscv/
Dpanic_arch.c124 const uint32_t core0_status = REG_READ(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG); in print_cache_err_details() local
128 bool handled = test_and_print_register_bits(core0_status, core0_acs_bits, DIM(core0_acs_bits)); in print_cache_err_details()
140 panic_print_hex(core0_status); in print_cache_err_details()