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Searched refs:SENS_SAR_TSENS_CTRL_REG (Results 1 – 6 of 6) sorted by relevance

/hal_espressif-3.6.0/components/esp_hw_support/test/
Dtest_tsens.c19 SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
20 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
21 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
22 SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
23 SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
25 SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
/hal_espressif-3.6.0/examples/system/deep_sleep/main/
Ddeep_sleep_example_main.c340 SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 2, SENS_TSENS_CLK_DIV_S); in start_ulp_temperature_monitoring()
342 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP); in start_ulp_temperature_monitoring()
343 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT); in start_ulp_temperature_monitoring()
344 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE); in start_ulp_temperature_monitoring()
/hal_espressif-3.6.0/components/ulp/test/esp32/
Dtest_ulp.c343 SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
345 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
346 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
347 CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dsens_reg.h404 #define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x004c) macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsens_reg.h500 #define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x0050) macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsens_reg.h483 #define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x50) macro