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Searched refs:REGS (Results 1 – 22 of 22) sorted by relevance

/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32/
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
38 if addr == self.REGS.APB_CTL_DATE_ADDR:
39 return self.REGS.APB_CTL_DATE_V << self.REGS.APB_CTL_DATE_S
42 if addr == self.REGS.EFUSE_BLK0_RDATA3_REG:
43 val = self.REGS.EFUSE_RD_CHIP_VER_REV1
44 if addr == self.REGS.EFUSE_BLK0_RDATA5_REG:
45 val = self.REGS.EFUSE_RD_CHIP_VER_REV2
52 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
54 if self.read_reg(self.REGS.EFUSE_REG_CMD) == 0:
60 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_WRITE)
[all …]
Dfields.py25 parent.coding_scheme = parent.REGS.CODING_SCHEME_NONE
33 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_34:
70 REGS = EfuseDefineRegisters variable in EspEfuses
118 if self.coding_scheme == self.REGS.CODING_SCHEME_NONE:
125 elif self.coding_scheme == self.REGS.CODING_SCHEME_34:
191 self.read_efuse(self.REGS.EFUSE_CODING_SCHEME_WORD)
192 & self.REGS.EFUSE_CODING_SCHEME_MASK
199 "EFUSE_REG_DEC_STATUS", self.read_reg(self.REGS.EFUSE_REG_DEC_STATUS)
210 clk_sel0, clk_sel1, dac_clk_div = self.REGS.EFUSE_CLK_SETTINGS[apb_freq]
213 self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_MASK, dac_clk_div
[all …]
Doperations.py273 if efuses.coding_scheme == efuses.REGS.CODING_SCHEME_34:
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s2/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
145 self.coding_scheme = self.REGS.CODING_SCHEME_RS
152 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
157 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
177 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
182 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
185 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c2/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
139 self.coding_scheme = self.REGS.CODING_SCHEME_RS
146 "EFUSE_RD_RS_ERR_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR_REG)
166 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
171 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
174 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
182 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
183 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
190 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)
[all …]
Demulate_efuse_controller.py23 REGS = EfuseDefineRegisters variable in EmulateEfuseController
27 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
52 if addr == self.REGS.EFUSE_CMD_REG:
53 if value & self.REGS.EFUSE_PGM_CMD:
58 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
59 elif value == self.REGS.EFUSE_READ_CMD:
61 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32h2beta1/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
139 self.coding_scheme = self.REGS.CODING_SCHEME_RS
146 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
151 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
171 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
176 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
179 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
187 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
188 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c6/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
145 self.coding_scheme = self.REGS.CODING_SCHEME_RS
152 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
157 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
177 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
182 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
185 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32h2/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
145 self.coding_scheme = self.REGS.CODING_SCHEME_RS
152 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
157 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
177 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
182 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
185 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c3/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
145 self.coding_scheme = self.REGS.CODING_SCHEME_RS
152 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
157 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
177 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
182 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
185 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s3beta2/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
145 self.coding_scheme = self.REGS.CODING_SCHEME_RS
152 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
157 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
177 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
182 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
185 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s3/
Dfields.py37 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
59 REGS = EfuseDefineRegisters variable in EspEfuses
145 self.coding_scheme = self.REGS.CODING_SCHEME_RS
152 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
157 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
177 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
182 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
185 if self.read_reg(self.REGS.EFUSE_STATUS_REG) & 0x7 == 1:
193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
[all …]
Demulate_efuse_controller.py21 REGS = EfuseDefineRegisters variable in EmulateEfuseController
25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
50 if addr == self.REGS.EFUSE_CMD_REG:
51 if value & self.REGS.EFUSE_PGM_CMD:
56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
57 elif value == self.REGS.EFUSE_READ_CMD:
59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/
Demulate_efuse_controller_base.py20 REGS = None variable in EmulateEfuseControllerBase
29 length=self.REGS.EFUSE_MEM_SIZE * 8,
33 self.mem = BitStream(length=self.REGS.EFUSE_MEM_SIZE * 8)
39 self.mem = BitStream(self.REGS.EFUSE_MEM_SIZE * 8)
58 self.mem.pos = self.mem.length - ((addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + 32)
62 self.mem.pos = self.mem.length - ((addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + 32)
67 position = self.mem.length - ((addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + 32)
141 (addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + blk_len_bits
153 (blk.rd_addr - self.REGS.DR_REG_EFUSE_BASE) * 8 + wr_data.len
Dbase_fields.py173 if coding_scheme == self.parent.REGS.CODING_SCHEME_NONE:
175 elif coding_scheme == self.parent.REGS.CODING_SCHEME_34:
177 elif coding_scheme == self.parent.REGS.CODING_SCHEME_RS:
186 return self.parent.REGS.CODING_SCHEME_NONE
282 if coding_scheme == self.parent.REGS.CODING_SCHEME_NONE:
284 elif coding_scheme == self.parent.REGS.CODING_SCHEME_RS:
291 elif coding_scheme == self.parent.REGS.CODING_SCHEME_34:
Dbase_operations.py367 != efuses.REGS.CODING_SCHEME_NONE