I2C_INT_STATUS_REG (reference) in projects: hal_espressif-3.6.0

/hal_espressif-3.6.0/components/soc/esp32/include/soc/

/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/

/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/

/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/

/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/

/hal_espressif-3.6.0/components/soc/esp32/include/soc/
D	i2c_reg.h	`525 #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) macro`
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
D	i2c_reg.h	`627 #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) macro`
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
D	i2c_reg.h	`627 #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) macro`
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
D	i2c_reg.h	`785 #define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) macro`
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
D	i2c_reg.h	`626 #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
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babblesim_base-3.4.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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cmsis-2.7.6
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cmsis-3.7.0-3.6.0
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zcbor-3.5.0-3.4.0
zcbor-3.6.0
zcbor-3.7.0
zscilib-3.4.0

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