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Searched refs:GET_PERI_REG_MASK (Results 1 – 25 of 25) sorted by relevance

/hal_espressif-3.6.0/components/esp_hw_support/port/esp32s2/
Drtc_time.c41 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal_oneoff()
47 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal_oneoff()
48 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal_oneoff()
82 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal_oneoff()
86 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal_oneoff()
108 …if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYC… in rtc_clk_cal_internal_cycling()
117 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_CYCLING_DATA_VLD)); in rtc_clk_cal_internal_cycling()
253 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
Drtc_sleep.c115 if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { in rtc_sleep_init()
168 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, in rtc_sleep_start()
Drtc_clk.c119 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in rtc_clk_8m_enabled()
124 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in rtc_clk_8md256_enabled()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32c3/
Drtc_time.c64 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
70 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
71 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
101 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
105 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
180 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
Drtc_sleep.c115 if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { in rtc_sleep_init()
165 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, in rtc_sleep_start()
Drtc_clk.c108 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in rtc_clk_8m_enabled()
113 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in rtc_clk_8md256_enabled()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32h2/
Drtc_time.c60 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
66 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
67 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
97 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
101 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
172 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
Drtc_sleep.c241 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, in rtc_sleep_start()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32s3/
Drtc_time.c66 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
72 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
73 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
107 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
111 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
186 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
Drtc_clk.c118 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in rtc_clk_8m_enabled()
123 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in rtc_clk_8md256_enabled()
Drtc_sleep.c292 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, in rtc_sleep_start()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32/
Drtc_time.c92 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) && in rtc_clk_cal_internal()
145 while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { in rtc_time_get()
165 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_wait_for_slow_cycle()
Drtc_sleep.c189 if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { in rtc_sleep_init()
233 while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, in rtc_sleep_start()
Drtc_clk.c240 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0; in rtc_clk_32k_enabled()
263 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in rtc_clk_8m_enabled()
268 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in rtc_clk_8md256_enabled()
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32s3/
Dcache_err_int.c110 if (GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, pro_mask)) { in esp_cache_err_get_cpuid()
120 if (GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, app_mask)) { in esp_cache_err_get_cpuid()
/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Drtc_cntl_ll.h37 return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); in rtc_cntl_ll_gpio_get_wakeup_pins()
/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h37 return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); in rtc_cntl_ll_gpio_get_wakeup_pins()
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsoc.h221 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
222 …ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); …
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dsoc.h192 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
193 …ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); …
/hal_espressif-3.6.0/components/soc/src/esp32/
Drtc_clk.c205 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0; in rtc_clk_32k_enabled()
228 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in rtc_clk_8m_enabled()
233 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in rtc_clk_8md256_enabled()
/hal_espressif-3.6.0/components/ulp/ulp_riscv/include/ulp_riscv/
Dulp_riscv_register_ops.h124 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsoc.h176 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsoc.h199 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsoc.h209 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
/hal_espressif-3.6.0/zephyr/esp32s3/src/wifi/
Desp_wifi_adapter.c499 if (GET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL)) { in esp_clk_slowclk_cal_get_wrapper()