Searched refs:EXTMEM_ICACHE_CTRL1_REG (Results 1 – 9 of 9) sorted by relevance
/hal_espressif-3.6.0/zephyr/esp32c3/src/boot/ |
D | bootloader_init.c | 92 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu() 93 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
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/hal_espressif-3.6.0/components/bootloader_support/src/esp32h2/ |
D | bootloader_esp32h2.c | 81 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu() 82 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
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/hal_espressif-3.6.0/components/bootloader_support/src/esp32c3/ |
D | bootloader_esp32c3.c | 82 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu() 83 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
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/hal_espressif-3.6.0/zephyr/esp32s3/src/boot/ |
D | bootloader_init.c | 60 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS); in bootloader_reset_mmu() 61 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS); in bootloader_reset_mmu()
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/hal_espressif-3.6.0/components/bootloader_support/src/esp32s3/ |
D | bootloader_esp32s3.c | 81 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS); in bootloader_reset_mmu() 83 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS); in bootloader_reset_mmu()
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/hal_espressif-3.6.0/components/bootloader_support/src/ |
D | bootloader_utility.c | 811 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); 812 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); 814 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); 815 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/ |
D | extmem_reg.h | 30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) macro
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/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/ |
D | extmem_reg.h | 30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) macro
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/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/ |
D | extmem_reg.h | 405 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) macro
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