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Searched refs:EFUSE_WR_TIM_CONF0_REG (Results 1 – 6 of 6) sorted by relevance

/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32c2/
Dmem_definition.py43 EFUSE_WR_TIM_CONF0_REG = DR_REG_EFUSE_BASE + 0x110 variable in EfuseDefineRegisters
Dfields.py247 self.REGS.EFUSE_WR_TIM_CONF0_REG,
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32s2/
Dfields.py257 self.REGS.EFUSE_WR_TIM_CONF0_REG, self.REGS.EFUSE_TPGM_M, EFUSE_TPGM
260 self.REGS.EFUSE_WR_TIM_CONF0_REG, self.REGS.EFUSE_THP_A_M, EFUSE_THP_A
263 self.REGS.EFUSE_WR_TIM_CONF0_REG,
Dmem_definition.py68 EFUSE_WR_TIM_CONF0_REG = DR_REG_EFUSE_BASE + 0x1F0 variable in EfuseDefineRegisters
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Defuse_reg.h1907 #define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Defuse_reg.h2262 #define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) macro