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Searched refs:DR_REG_SYSCON_BASE (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsyscon_reg.h22 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
30 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010)
38 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
46 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020)
54 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
62 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C)
70 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030)
78 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034)
86 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038)
94 #define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C)
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Dsoc.h81 #define DR_REG_SYSCON_BASE 0x60026000 macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsyscon_reg.h23 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
49 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
69 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8)
137 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
145 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
153 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14)
161 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
225 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
233 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
241 #define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x24)
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Dsoc.h75 #define DR_REG_SYSCON_BASE 0x60026000 macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsyscon_reg.h22 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
42 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
62 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
130 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x00C)
138 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x010)
146 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x014)
154 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x018)
162 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x01C)
170 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x020)
178 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x024)
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Dsoc.h78 #define DR_REG_SYSCON_BASE 0x3f426000 macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsyscon_reg.h22 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
48 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
68 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
136 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
144 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010)
152 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014)
160 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018)
220 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
228 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020)
236 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
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Dsoc.h63 #define DR_REG_SYSCON_BASE 0x60026000 macro
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dsyscon_reg.h18 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
50 #define SYSCON_XTAL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
58 #define SYSCON_PLL_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x8)
66 #define SYSCON_CK8M_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0xC)
74 #define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x10)
157 #define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x14)
183 #define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x18)
209 #define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x1C)
217 #define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x20)
225 #define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x24)
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Dsoc.h75 #define DR_REG_SYSCON_BASE 0x3ff66000 macro
/hal_espressif-3.6.0/components/esptool_py/esptool/espefuse/efuse/esp32/
Dmem_definition.py47 DR_REG_SYSCON_BASE = 0x3FF66000 variable in EfuseDefineRegisters
48 APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE + 0x7C
/hal_espressif-3.6.0/components/esptool_py/esptool/esptool/targets/
Desp32.py51 DR_REG_SYSCON_BASE = 0x3FF66000 variable in ESP32ROM
52 APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE + 0x7C