Home
last modified time | relevance | path

Searched refs:DR_REG_SLCHOST_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dhost_reg.h23 #define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
31 #define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
39 #define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
47 #define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C)
55 #define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
63 #define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
89 #define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
97 #define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
255 #define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
413 #define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
[all …]
Dsoc.h56 #define DR_REG_SLCHOST_BASE 0x60015000 macro
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dhost_reg.h19 #define HOST_SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
27 #define HOST_SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14)
35 #define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
43 #define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
51 #define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
59 #define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C)
67 #define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
75 #define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
101 #define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
109 #define HOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4C)
[all …]
Dsoc.h58 #define DR_REG_SLCHOST_BASE 0x3ff55000 macro
/hal_espressif-3.6.0/components/sdmmc/test/
Dtest_sdio.c58 #define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64)
59 #define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C)
60 #define SLCHOST_CONF_W5 (DR_REG_SLCHOST_BASE + 0x80)
61 #define SLCHOST_WIN_CMD (DR_REG_SLCHOST_BASE + 0x84)
73 if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) { in slave_slchost_reg_read()
82 if ((addr & DR_REG_SLCHOST_MASK) != DR_REG_SLCHOST_BASE) { in slave_slchost_reg_write()
289 const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE; in test_cmd52_read_write_single_byte()
315 const size_t scratch_area_reg = SLCHOST_CONF_W0 - DR_REG_SLCHOST_BASE; in test_cmd53_read_write_multiple_bytes()
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsoc.h67 #define DR_REG_SLCHOST_BASE 0x60019000 macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsoc.h63 #define DR_REG_SLCHOST_BASE 0x3f415000 macro