DR_REG_SENSITIVE_BASE (reference) in projects: hal_espressif-3.6.0

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Searched refs:DR_REG_SENSITIVE_BASE (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
D	sensitive_reg.h	22 #define DPORT_PMS_SDIO_0_REG (DR_REG_SENSITIVE_BASE + 0x000) 30 #define DPORT_PMS_SDIO_1_REG (DR_REG_SENSITIVE_BASE + 0x004) 38 #define DPORT_PMS_MAC_DUMP_0_REG (DR_REG_SENSITIVE_BASE + 0x008) 46 #define DPORT_PMS_MAC_DUMP_1_REG (DR_REG_SENSITIVE_BASE + 0x00C) 54 #define DPORT_PMS_PRO_IRAM0_0_REG (DR_REG_SENSITIVE_BASE + 0x010) 62 #define DPORT_PMS_PRO_IRAM0_1_REG (DR_REG_SENSITIVE_BASE + 0x014) 136 #define DPORT_PMS_PRO_IRAM0_2_REG (DR_REG_SENSITIVE_BASE + 0x018) 180 #define DPORT_PMS_PRO_IRAM0_3_REG (DR_REG_SENSITIVE_BASE + 0x01C) 224 #define DPORT_PMS_PRO_IRAM0_4_REG (DR_REG_SENSITIVE_BASE + 0x020) 244 #define DPORT_PMS_PRO_IRAM0_5_REG (DR_REG_SENSITIVE_BASE + 0x024) [all …]
D	soc.h	`28 #define DR_REG_SENSITIVE_BASE 0x3f4c1000 macro`
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
D	sensitive_reg.h	23 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG (DR_REG_SENSITIVE_BASE + 0x0) 31 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG (DR_REG_SENSITIVE_BASE + 0x4) 39 #define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8) 47 #define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xC) 55 #define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10) 63 #define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14) 83 #define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG (DR_REG_SENSITIVE_BASE + 0x18) 109 #define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x1C) 117 #define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x20) 125 #define SENSITIVE_RETENTION_DISABLE_REG (DR_REG_SENSITIVE_BASE + 0x24) [all …]
D	soc.h	`99 #define DR_REG_SENSITIVE_BASE 0x600C1000 macro`
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
D	sensitive_reg.h	22 #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) 30 #define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x004) 38 #define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x008) 46 #define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0x00C) 54 #define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x010) 62 #define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x014) 70 #define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x018) 78 #define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x01C) 92 #define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x020) 106 #define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x024) [all …]
D	soc.h	`28 #define DR_REG_SENSITIVE_BASE 0x600c1000 macro`
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
D	sensitive_reg.h	22 #define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x000) 30 #define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x004) 38 #define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x008) 46 #define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0x00C) 54 #define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x010) 62 #define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x014) 70 #define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x018) 78 #define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x01C) 92 #define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x020) 106 #define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x024) [all …]
D	soc.h	`28 #define DR_REG_SENSITIVE_BASE 0x600c1000 macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
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