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Searched refs:DR_REG_INTERRUPT_BASE (Results 1 – 11 of 11) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dinterrupt_reg.h22 #define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x000)
30 #define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x004)
38 #define DPORT_PRO_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x008)
46 #define DPORT_PRO_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x00C)
54 #define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x010)
62 #define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x014)
70 #define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x018)
78 #define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x01C)
86 #define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x020)
94 #define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x024)
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Dsoc.h29 #define DR_REG_INTERRUPT_BASE 0x3f4c2000 macro
/hal_espressif-3.6.0/components/riscv/
Dinterrupt.c74 REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num); in intr_matrix_route()
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsoc.h29 #define DR_REG_INTERRUPT_BASE 0x600c2000 macro
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsoc.h29 #define DR_REG_INTERRUPT_BASE 0x600c2000 macro
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsoc.h100 #define DR_REG_INTERRUPT_BASE 0x600C2000 macro
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
Dinterrupt_core1_reg.h23 #define DR_REG_INTERRUPT_CORE1_BASE DR_REG_INTERRUPT_BASE
/hal_espressif-3.6.0/zephyr/esp32c3/src/wifi/
Desp_wifi_adapter.c548 REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_source, intr_num); in set_intr_wrapper()