Searched refs:CONFIG_ETH_DMA_RX_BUFFER_NUM (Results 1 – 20 of 20) sorted by relevance
157 CONFIG_ETH_DMA_RX_BUFFER_NUM); in emac_hal_reset_desc_chain()159 for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) { in emac_hal_reset_desc_chain()173 hal->rx_desc[CONFIG_ETH_DMA_RX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc); in emac_hal_reset_desc_chain()467 …ter->RDES0.Own != EMAC_LL_DMADESC_OWNER_DMA) && (used_descs < CONFIG_ETH_DMA_RX_BUFFER_NUM) && !fr… in emac_hal_receive_frame()489 …esc_iter->RDES0.Own != EMAC_LL_DMADESC_OWNER_DMA) && (used_descs < CONFIG_ETH_DMA_RX_BUFFER_NUM)) { in emac_hal_receive_frame()519 *free_desc = CONFIG_ETH_DMA_RX_BUFFER_NUM - used_descs; in emac_hal_receive_frame()
37 #define FLOW_CONTROL_LOW_WATER_MARK (CONFIG_ETH_DMA_RX_BUFFER_NUM / 3)55 uint8_t *rx_buf[CONFIG_ETH_DMA_RX_BUFFER_NUM];447 for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) { in esp_emac_free_driver_obj()474 uint32_t desc_size = CONFIG_ETH_DMA_RX_BUFFER_NUM * sizeof(eth_dma_rx_descriptor_t) + in esp_emac_alloc_driver_obj()479 for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) { in esp_emac_alloc_driver_obj()
119 #define CONFIG_ETH_DMA_RX_BUFFER_NUM 10 macro
104 …guration options are :ref:`CONFIG_ETH_DMA_BUFFER_SIZE`, :ref:`CONFIG_ETH_DMA_RX_BUFFER_NUM`, :ref:…
1305 CONFIG_ETH_DMA_RX_BUFFER_NUM=10
1290 CONFIG_ETH_DMA_RX_BUFFER_NUM=10
1302 CONFIG_ETH_DMA_RX_BUFFER_NUM=10
1300 CONFIG_ETH_DMA_RX_BUFFER_NUM=10
1304 CONFIG_ETH_DMA_RX_BUFFER_NUM=10
