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Searched refs:AES_XTS_STATE_REG (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Dspi_flash_encrypted_ll.h122 while(REG_READ(AES_XTS_STATE_REG) == 0x1) { in spi_flash_encrypt_ll_calculate_wait_idle()
132 while(REG_READ(AES_XTS_STATE_REG) != 0x3) { in spi_flash_encrypt_ll_done()
/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dspi_flash_encrypted_ll.h122 while(REG_READ(AES_XTS_STATE_REG) == 0x1) { in spi_flash_encrypt_ll_calculate_wait_idle()
132 while(REG_READ(AES_XTS_STATE_REG) != 0x3) { in spi_flash_encrypt_ll_done()
/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Dspi_flash_encrypted_ll.h122 while(REG_READ(AES_XTS_STATE_REG) == 0x1) { in spi_flash_encrypt_ll_calculate_wait_idle()
132 while(REG_READ(AES_XTS_STATE_REG) != 0x3) { in spi_flash_encrypt_ll_done()
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Dspi_flash_encrypted_ll.h131 while(REG_READ(AES_XTS_STATE_REG) == 0x1) { in spi_flash_encrypt_ll_calculate_wait_idle()
141 while(REG_READ(AES_XTS_STATE_REG) != 0x3) { in spi_flash_encrypt_ll_done()
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h124 #define AES_XTS_STATE_REG ((DR_REG_EXT_MEM_ENC) + 0x58) macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h161 #define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58) macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dhwcrypto_reg.h161 #define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58) macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h173 #define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0x158) macro