| /hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/GPIO/ |
| D | gpio_reva.c | 170 port->en0_clr = mask; in MXC_GPIO_RevA_SetAF()
177 port->en0_clr = mask; in MXC_GPIO_RevA_SetAF()
185 port->en0_clr = mask; in MXC_GPIO_RevA_SetAF()
192 port->en0_clr = mask; in MXC_GPIO_RevA_SetAF()
200 port->en0_clr = mask; in MXC_GPIO_RevA_SetAF()
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| D | gpio_revb.c | 51 gpio->en0_clr = cfg->mask; in MXC_GPIO_RevB_Config()
57 gpio->en0_clr = cfg->mask; in MXC_GPIO_RevB_Config()
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| D | gpio_me11.c | 88 gpio->en0_clr = cfg->mask; in MXC_GPIO_Config()
94 gpio->en0_clr = cfg->mask; in MXC_GPIO_Config()
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| D | gpio_reva_regs.h | 77 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO_REVA EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Include/ |
| D | gpio_regs.h | 78 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Include/ |
| D | gpio_regs.h | 79 __IO uint32_t en0_clr; /**< <tt>\b 0x08:</tt> GPIO EN0_CLR Register */ member
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| /hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SPIXF/ |
| D | spixf_me55.c | 66 port->en0_clr = cfg->mask; in MXC_GPIO_Config_SPIXF()
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| /hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/AFE/ |
| D | hart_uart.c | 617 HART_CLK_GPIO_PORT->en0_clr = HART_CLK_GPIO_PIN; in hart_clock_enable()
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