Home
last modified time | relevance | path

Searched refs:CoreDebug_DHCSR_S_RESTART_ST_Pos (Results 1 – 8 of 8) sorted by relevance

/cmsis-latest/CMSIS/Core/Include/
Dcore_cm23.h1081 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1082 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_armv8mbl.h1006 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1007 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_cm35p.h1826 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1827 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_cm33.h1826 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1827 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_armv8mml.h1751 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1752 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_armv81mml.h2638 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
2639 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_cm85.h3039 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
3040 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
Dcore_cm55.h3134 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
3135 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…