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Searched refs:trailing_clocks (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/drivers/fpga/
Dfpga_ice40_common.h39 BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) >= FPGA_ICE40_TRAILING_CLOCKS_MIN); \
40 BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) <= UINT8_MAX); \
52 .trailing_clocks = DT_INST_PROP(inst, trailing_clocks), \
72 uint8_t trailing_clocks; member
Dfpga_ice40_spi.c135 LOG_DBG("Send %u clocks", config->trailing_clocks); in fpga_ice40_load()
137 tx_buf.len = DIV_ROUND_UP(config->trailing_clocks, BITS_PER_BYTE); in fpga_ice40_load()
140 LOG_ERR("Failed to send trailing %u clocks: %d", config->trailing_clocks, ret); in fpga_ice40_load()
Dfpga_ice40_bitbang.c206 LOG_DBG("Send %u clocks", config->trailing_clocks); in fpga_ice40_load()
208 config_bitbang->clear, clk, config->trailing_clocks); in fpga_ice40_load()