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Searched refs:pllcx_div (Results 1 – 1 of 1) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_agilex5_ll.c74 uint32_t pllcx_div = 0U; in get_clk_freq() local
84 pllcx_div = (sys_read32(mainpllc_reg) & CLKCTRL_PLLCX_DIV_MSK); in get_clk_freq()
85 __ASSERT(pllcx_div != 0, "Main PLLC clock divider is zero"); in get_clk_freq()
86 clock_val /= pllcx_div; in get_clk_freq()
91 pllcx_div = (sys_read32(perpllc_reg) & CLKCTRL_PLLCX_DIV_MSK); in get_clk_freq()
92 __ASSERT(pllcx_div != 0, "Peripheral PLLC clock divider is zero"); in get_clk_freq()
93 clock_val /= pllcx_div; in get_clk_freq()