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Searched refs:RCU_CFG0_APB2PSC_POS (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/soc/gd/gd32/gd32l23x/
Dgd32_regs.h21 #define RCU_CFG0_APB2PSC_POS 11U macro
22 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dgd32_regs.h22 #define RCU_CFG0_APB2PSC_POS 11U macro
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32e10x/
Dgd32_regs.h22 #define RCU_CFG0_APB2PSC_POS 11U macro
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32e50x/
Dgd32_regs.h22 #define RCU_CFG0_APB2PSC_POS 11U macro
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32f3x0/
Dgd32_regs.h22 #define RCU_CFG0_APB2PSC_POS 11U macro
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32f403/
Dgd32_regs.h22 #define RCU_CFG0_APB2PSC_POS 11U macro
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32a50x/
Dgd32_regs.h23 #define RCU_CFG0_APB2PSC_POS 11U macro
24 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32f4xx/
Dgd32_regs.h25 #define RCU_CFG0_APB2PSC_POS 13U macro
26 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/drivers/clock_control/
Dclock_control_gd32.c126 psc = (cfg & RCU_CFG0_APB2PSC_MSK) >> RCU_CFG0_APB2PSC_POS; in clock_control_gd32_get_rate()