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/Zephyr-latest/arch/riscv/core/
Dipi_clint.c17 #define MSIP(hartid) ((volatile uint32_t *)MSIP_BASE)[hartid] macro
32 MSIP(_kernel.cpus[i].arch.hartid) = 1; in arch_sched_directed_ipi()
43 MSIP(_kernel.cpus[cpu].arch.hartid) = 1; in arch_flush_fpu_ipi()
51 MSIP(csr_read(mhartid)) = 0; in sched_ipi_handler()