HCLK_DIV_SEL (reference) in projects: Zephyr-latest

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Searched refs:HCLK_DIV_SEL (Results 1 – 1 of 1) sorted by relevance

/Zephyr-latest/drivers/clock_control/
D	clock_control_ast10x0.c	`43 #define HCLK_DIV_SEL GENMASK(30, 28) macro 118 clk_div = HCLK_DIV_REG_TO_VAL(FIELD_GET(HCLK_DIV_SEL, reg)); in aspeed_clock_control_get_rate()`