Home
last modified time | relevance | path

Searched refs:DT_PROP_OR (Results 1 – 25 of 100) sorted by relevance

1234

/Zephyr-latest/soc/adi/max32/common/
Dpinctrl_soc.h27 ((DT_PROP_OR(node, input_enable, 0) << MAX32_INPUT_ENABLE_SHIFT) | \
28 (DT_PROP_OR(node, output_enable, 0) << MAX32_OUTPUT_ENABLE_SHIFT) | \
29 (DT_PROP_OR(node, bias_pull_up, 0) << MAX32_BIAS_PULL_UP_SHIFT) | \
30 (DT_PROP_OR(node, bias_pull_down, 0) << MAX32_BIAS_PULL_DOWN_SHIFT) | \
31 (DT_PROP_OR(node, power_source, 0) << MAX32_POWER_SOURCE_SHIFT) | \
32 (DT_PROP_OR(node, output_high, 0) << MAX32_OUTPUT_HIGH_SHIFT) | \
33 (DT_PROP_OR(node, drive_strength, 0) << MAX32_DRV_STRENGTH_SHIFT))
/Zephyr-latest/include/zephyr/drivers/
Dregulator.h193 .min_uv = DT_PROP_OR(node_id, regulator_min_microvolt, \
195 .max_uv = DT_PROP_OR(node_id, regulator_max_microvolt, \
197 .init_uv = DT_PROP_OR(node_id, regulator_init_microvolt, \
199 .min_ua = DT_PROP_OR(node_id, regulator_min_microamp, \
201 .max_ua = DT_PROP_OR(node_id, regulator_max_microamp, \
203 .init_ua = DT_PROP_OR(node_id, regulator_init_microamp, \
205 .startup_delay_us = DT_PROP_OR(node_id, startup_delay_us, 0), \
206 .off_on_delay_us = DT_PROP_OR(node_id, off_on_delay_us, 0), \
208 DT_PROP_OR(node_id, regulator_allowed_modes, {}), \
211 .initial_mode = DT_PROP_OR(node_id, regulator_initial_mode, \
[all …]
Dadc.h249 (.input_positive = DT_PROP_OR(node_id, zephyr_input_positive, 0), \
250 .input_negative = DT_PROP_OR(node_id, zephyr_input_negative, 0),)) \
253 .current_source_pin = DT_PROP_OR(node_id, zephyr_current_source_pin, {0}),)) \
255 (.vbias_pins = DT_PROP_OR(node_id, zephyr_vbias_pins, 0),)) \
330 .vref_mv = DT_PROP_OR(node_id, zephyr_vref_mv, 0), \
331 .resolution = DT_PROP_OR(node_id, zephyr_resolution, 0), \
332 .oversampling = DT_PROP_OR(node_id, zephyr_oversampling, 0),))
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dadi_max32_clock_control.h40 #define ADI_MAX32_SYSCLK_PRESCALER DT_PROP_OR(DT_NODELABEL(gcr), sysclk_prescaler, 1)
43 #define ADI_MAX32_CLK_ERFO_FREQ DT_PROP_OR(DT_NODELABEL(clk_erfo), clock_frequency, 0)
45 #define ADI_MAX32_CLK_ISO_FREQ DT_PROP_OR(DT_NODELABEL(clk_iso), clock_frequency, 0)
48 #define ADI_MAX32_CLK_IPLL_FREQ DT_PROP_OR(DT_NODELABEL(clk_ipll), clock_frequency, 0)
49 #define ADI_MAX32_CLK_EBO_FREQ DT_PROP_OR(DT_NODELABEL(clk_ebo), clock_frequency, 0)
51 #define ADI_MAX32_CLK_EXTCLK_FREQ DT_PROP_OR(DT_NODELABEL(clk_extclk), clock_frequency, 0)
Dstm32_clock_control.h79 #define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
164 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
166 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
168 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
170 #define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
172 #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
180 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
188 #define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
190 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
200 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
[all …]
/Zephyr-latest/soc/nxp/mcx/mcxc/
Dflash_configuration.c32 DT_PROP_OR(DT_NODELABEL(ftfa), fsec, 0xFE),
37 DT_PROP_OR(DT_NODELABEL(ftfa), fopt, 0xFF),
Dsoc.c30 #define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
57 .fcrdiv = DT_PROP_OR(MCG_NODE, fcrdiv, 0),
59 .lircDiv2 = DT_PROP_OR(MCG_NODE, lircdiv2, 0),
/Zephyr-latest/include/zephyr/devicetree/
Dcan.h76 MAX(DT_PROP_OR(DT_PHANDLE(node_id, phys), min_bitrate, 0), min), \
77 MAX(DT_PROP_OR(DT_CHILD(node_id, can_transceiver), min_bitrate, min), min))
120 MIN(DT_PROP_OR(DT_CHILD(node_id, can_transceiver), max_bitrate, max), max))
/Zephyr-latest/include/zephyr/drivers/mspi/
Ddevicetree.h34 .ce_num = DT_PROP_OR(mspi_dev, mspi_hardware_ce_num, 0), \
46 .rx_dummy = DT_PROP_OR(mspi_dev, rx_dummy, 0), \
47 .tx_dummy = DT_PROP_OR(mspi_dev, tx_dummy, 0), \
48 .read_cmd = DT_PROP_OR(mspi_dev, read_command, 0), \
49 .write_cmd = DT_PROP_OR(mspi_dev, write_command, 0), \
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5_fem_generic.h35 DT_PROP_OR(FEM_NODE, ctx_settle_time_us, 0)
46 DT_PROP_OR(FEM_NODE, crx_settle_time_us, 0)
Dradio_df.h12 #define PDU_ANTENNA DT_PROP_OR(RADIO_NODE, dfe_pdu_antenna, 0)
/Zephyr-latest/include/zephyr/pm/
Dstate.h237 .substate_id = DT_PROP_OR(node_id, substate_id, 0), \
238 .min_residency_us = DT_PROP_OR(node_id, min_residency_us, 0), \
239 .exit_latency_us = DT_PROP_OR(node_id, exit_latency_us, 0), \
/Zephyr-latest/drivers/sensor/espressif/pcnt_esp32/
Dpcnt_esp32.c375 .filter = DT_PROP_OR(node_id, filter, 0) > 1024 ? 1024 \
376 : DT_PROP_OR(node_id, filter, 0), \
379 .sig_pos_mode = DT_PROP_OR(DT_CHILD(node_id, channela_0), \
381 .sig_neg_mode = DT_PROP_OR(DT_CHILD(node_id, channela_0), \
384 DT_PROP_OR(DT_CHILD(node_id, channela_0), ctrl_l_mode, 0), \
386 DT_PROP_OR(DT_CHILD(node_id, channela_0), ctrl_h_mode, 0), \
390 .sig_pos_mode = DT_PROP_OR(DT_CHILD(node_id, channelb_0), \
392 .sig_neg_mode = DT_PROP_OR(DT_CHILD(node_id, channelb_0), \
395 DT_PROP_OR(DT_CHILD(node_id, channelb_0), ctrl_l_mode, 0), \
397 DT_PROP_OR(DT_CHILD(node_id, channelb_0), ctrl_h_mode, 0), \
/Zephyr-latest/soc/nuvoton/numaker/m2l31x/
Dpoweroff.c20 CLK_SetPowerDownMode(DT_PROP_OR(DT_NODELABEL(scc), powerdown_mode, CLK_PMUCTL_PDMSEL_SPD0)); in z_sys_poweroff()
/Zephyr-latest/soc/nuvoton/numaker/m46x/
Dpoweroff.c20 CLK_SetPowerDownMode(DT_PROP_OR(DT_NODELABEL(scc), powerdown_mode, CLK_PMUCTL_PDMSEL_SPD)); in z_sys_poweroff()
/Zephyr-latest/drivers/dma/
Ddmamux_stm32.c311 #define DMA_1_BEGIN_DMAMUX_CHANNEL DT_PROP_OR(DT_NODELABEL(dma1), dma_offset, 0)
313 DT_PROP_OR(DT_NODELABEL(dma1), dma_requests, 0))
317 #define DMA_2_BEGIN_DMAMUX_CHANNEL DT_PROP_OR(DT_NODELABEL(dma2), dma_offset, 0)
319 DT_PROP_OR(DT_NODELABEL(dma2), dma_requests, 0))
323 #define BDMA_1_BEGIN_DMAMUX_CHANNEL DT_PROP_OR(DT_NODELABEL(bdma1), dma_offset, 0)
325 DT_PROP_OR(DT_NODELABEL(bdma1), dma_requests, 0))
/Zephyr-latest/modules/trusted-firmware-m/nordic/include/
Ddevice_cfg.h24 #define DEFAULT_UART_BAUDRATE DT_PROP_OR(DT_NODELABEL(TFM_UART), current_speed, 115200)
/Zephyr-latest/include/zephyr/drivers/pcie/
Dpcie.h74 #define PCIE_DT_ID(node_id) PCIE_ID(DT_PROP_OR(node_id, vendor_id, 0xffff), \
75 DT_PROP_OR(node_id, device_id, 0xffff))
100 .class_rev = DT_PROP_OR(node_id, class_rev, 0), \
101 .class_rev_mask = DT_PROP_OR(node_id, class_rev_mask, 0), \
/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_device_init_dcdc_config.h23 #define SL_DEVICE_INIT_DCDC_TYPE DT_PROP_OR(DCDC_NODE, regulator_initial_mode, 0)
/Zephyr-latest/drivers/gpio/
Dgpio_hogs.c39 DT_PROP_OR(node_id, gpio_controller, 0)
43 IF_ENABLED(DT_PROP_OR(node_id, gpio_hog, 0), 1)
/Zephyr-latest/include/zephyr/drivers/adc/
Dvoltage_divider.h31 .full_ohms = DT_PROP_OR(node_id, full_ohms, 0), \
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dpower.c17 DT_PROP_OR(NODE_ID, deep_sleep_config, {}))
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dmem_window.h21 #define WIN_OFFSET(n) (DT_PROP_OR(MEM_WINDOW_NODE(n), offset, (WIN##n##_OFFSET)))
/Zephyr-latest/include/zephyr/
Dcache.h414 return DT_PROP_OR(_CPU, d_cache_line_size, 0); in sys_cache_data_line_size_get()
441 return DT_PROP_OR(_CPU, i_cache_line_size, 0); in sys_cache_instr_line_size_get()
/Zephyr-latest/drivers/i2c/
Di2c_nrfx_twi_common.h25 I2C_NRFX_TWI_FREQUENCY(DT_PROP_OR(I2C(idx), clock_frequency, \

1234