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Searched refs:DMICSYNC_OFFSET (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic.c177 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
178 base + DMICSYNC_OFFSET); in dai_dmic_set_sync_period()
179 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, in dai_dmic_set_sync_period()
180 base + DMICSYNC_OFFSET); in dai_dmic_set_sync_period()
182 if (!WAIT_FOR((sys_read32(base + DMICSYNC_OFFSET) & DMICSYNC_SYNCPU) == 0, 1000, in dai_dmic_set_sync_period()
187 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, in dai_dmic_set_sync_period()
188 base + DMICSYNC_OFFSET); in dai_dmic_set_sync_period()
190 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
191 base + DMICSYNC_OFFSET); in dai_dmic_set_sync_period()
192 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, in dai_dmic_set_sync_period()
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Ddmic_regs_ace2x.h12 #define DMICSYNC_OFFSET 0x1C macro
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Ddmic_regs_ace3x.h10 #define DMICSYNC_OFFSET 0x1C macro
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Ddmic_regs_ace1x.h52 #define DMICSYNC_OFFSET 0x0C macro