Home
last modified time | relevance | path

Searched refs:APBSRC_CLK (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_npcx.c174 BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
175 APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
178 BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
179 APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
182 BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
183 APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
187 BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MAX_OFMCLK &&
188 APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
196 BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(20),
Dclock_control_npcm.c112 #define APBSRC_CLK OFMCLK macro
118 #define NPCM_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h84 #define APBSRC_CLK OFMCLK macro
119 #define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))