Searched refs:ADXL367_FIFO_CONTROL (Results 1 – 3 of 3) sorted by relevance
471 ret = data->hw_tf->write_reg_mask(dev, ADXL367_FIFO_CONTROL, in adxl367_set_fifo_sample_sets_nb()501 ADXL367_FIFO_CONTROL, in adxl367_set_fifo_mode()555 ADXL367_FIFO_CONTROL, in adxl367_set_fifo_format()
48 const uint8_t reg_addr_w2[3] = {ADXL367_SPI_WRITE_REG, ADXL367_FIFO_CONTROL, in adxl367_fifo_flush_rtio()54 const uint8_t reg_addr_w3[3] = {ADXL367_SPI_WRITE_REG, ADXL367_FIFO_CONTROL, in adxl367_fifo_flush_rtio()
83 #define ADXL367_FIFO_CONTROL 0x28u /* FIFO Control */ macro