Searched refs:div1 (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-Core-3.7.0/soc/openisa/rv32m1/ |
| D | soc.c | 34 .div1 = kSCG_AsyncClkDivBy1,
57 .div1 = kSCG_AsyncClkDivBy1,
179 .div1 = kSCG_AsyncClkDisable, in rv32m1_switch_to_sirc()
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 74 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv1_clk)),
87 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv1_clk)),
105 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv1_clk)),
135 .div1 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv1_clk)),
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| /Zephyr-Core-3.7.0/drivers/ethernet/ |
| D | eth_xlnx_gem.c | 735 uint32_t div1; in eth_xlnx_gem_configure_clocks() local
776 for (div1 = 1; div1 < 64; div1++) { in eth_xlnx_gem_configure_clocks()
777 tmp = ((dev_conf->pll_clock_frequency / div0) / div1); in eth_xlnx_gem_configure_clocks()
803 ((div1 & ETH_XLNX_CRL_APB_GEMX_REF_CTRL_DIVISOR_MASK) << in eth_xlnx_gem_configure_clocks()
829 ((div1 & ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK) << in eth_xlnx_gem_configure_clocks()
836 "frequency %u Hz", dev->name, div0, div1, target); in eth_xlnx_gem_configure_clocks()
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| /Zephyr-Core-3.7.0/dts/arm/rpi_pico/ |
| D | rp2040.dtsi | 125 post-div1 = <6>;
136 post-div1 = <5>;
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