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Searched refs:STM32_PLL_M_DIVISOR (Results 1 – 10 of 10) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_stm32g4.c66 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32g0.c62 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_wba.c219 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
225 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
231 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
388 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); in set_up_plls()
393 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_u5.c107 STM32_PLL_M_DIVISOR, in get_sysclk_frequency()
291 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
297 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
303 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
463 tmp = MIN(tmp / STM32_PLL_M_DIVISOR / 8000000, 16); in set_epod_booster()
540 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
545 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h5.c103 STM32_PLL_M_DIVISOR, in get_sysclk_frequency()
277 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
283 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
289 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
453 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
460 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32l4_l5_wb_wl.c81 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32f2_f4_f7.c63 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_h7.c75 STM32_PLL_M_DIVISOR,\
241 STM32_PLL_M_DIVISOR, in get_hclk_frequency()
555 STM32_PLL_M_DIVISOR,
561 STM32_PLL_M_DIVISOR,
567 STM32_PLL_M_DIVISOR,
574 STM32_PLL_M_DIVISOR,
788 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
795 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR);
Dclock_stm32_ll_common.c383 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
391 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
399 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
/Zephyr-Core-3.7.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h151 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) macro
167 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR