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Searched refs:PL011_CR_RTSEn (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/serial/
Duart_pl011_registers.h105 #define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */ macro
Duart_pl011.c94 get_uart(dev)->cr |= PL011_CR_RTSEn; in pl011_set_flow_control()
96 get_uart(dev)->cr &= ~PL011_CR_RTSEn; in pl011_set_flow_control()