1 /* 2 * Copyright (c) 2023 Analog Devices Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ 9 10 #include <zephyr/drivers/sensor.h> 11 #include <zephyr/types.h> 12 #include <zephyr/device.h> 13 #include <zephyr/drivers/gpio.h> 14 #include <zephyr/kernel.h> 15 #include <zephyr/sys/util.h> 16 17 #define DT_DRV_COMPAT adi_adxl367 18 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 19 #define ADXL367_BUS_SPI 20 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 21 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 22 #define ADXL367_BUS_I2C 23 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 24 #undef DT_DRV_COMPAT 25 26 #define DT_DRV_COMPAT adi_adxl366 27 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 28 #define ADXL367_BUS_SPI 29 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 30 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 31 #define ADXL367_BUS_I2C 32 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 33 #undef DT_DRV_COMPAT 34 35 #ifdef ADXL367_BUS_SPI 36 #include <zephyr/drivers/spi.h> 37 #endif /* ADXL367_BUS_SPI */ 38 39 #ifdef ADXL367_BUS_I2C 40 #include <zephyr/drivers/i2c.h> 41 #endif /* ADXL367_BUS_I2C */ 42 43 #define ADXL367_CHIP_ID 0 44 #define ADXL366_CHIP_ID 1 45 46 /* 47 * ADXL367 registers definition 48 */ 49 #define ADXL367_DEVID 0x00u /* Analog Devices accelerometer ID */ 50 #define ADXL367_DEVID_MST 0x01u /* Analog Devices MEMS device ID */ 51 #define ADXL367_PART_ID 0x02u /* Device ID */ 52 #define ADXL367_REV_ID 0x03u /* product revision ID*/ 53 #define ADXL367_SERIAL_NR_3 0x04u /* Serial Number 3 */ 54 #define ADXL367_SERIAL_NR_2 0x05u /* Serial Number 2 */ 55 #define ADXL367_SERIAL_NR_1 0x06u /* Serial Number 1 */ 56 #define ADXL367_SERIAL_NR_0 0x07u /* Serial Number 0 */ 57 #define ADXL367_XDATA 0x08u /* X-axis acceleration data [13:6] */ 58 #define ADXL367_YDATA 0x09u /* Y-axis acceleration data [13:6] */ 59 #define ADXL367_ZDATA 0x0Au /* Z-axis acceleration data [13:6] */ 60 #define ADXL367_STATUS 0x0Bu /* Status */ 61 #define ADXL367_FIFO_ENTRIES_L 0x0Cu /* FIFO Entries Low */ 62 #define ADXL367_FIFO_ENTRIES_H 0x0Du /* FIFO Entries High */ 63 #define ADXL367_X_DATA_H 0x0Eu /* X-axis acceleration data [13:6] */ 64 #define ADXL367_X_DATA_L 0x0Fu /* X-axis acceleration data [5:0] */ 65 #define ADXL367_Y_DATA_H 0x10u /* Y-axis acceleration data [13:6] */ 66 #define ADXL367_Y_DATA_L 0x11u /* Y-axis acceleration data [5:0] */ 67 #define ADXL367_Z_DATA_H 0x12u /* Z-axis acceleration data [13:6] */ 68 #define ADXL367_Z_DATA_L 0x13u /* Z-axis acceleration data [5:0] */ 69 #define ADXL367_TEMP_H 0x14u /* Temperate data [13:6] */ 70 #define ADXL367_TEMP_L 0x15u /* Temperate data [5:0] */ 71 #define ADXL367_EX_ADC_H 0x16u /* Extended ADC data [13:6] */ 72 #define ADXL367_EX_ADC_L 0x17u /* Extended ADC data [5:0] */ 73 #define ADXL367_I2C_FIFO_DATA 0x18u /* I2C FIFO Data address */ 74 #define ADXL367_SOFT_RESET 0x1Fu /* Software reset register */ 75 #define ADXL367_THRESH_ACT_H 0x20u /* Activity Threshold [12:6] */ 76 #define ADXL367_THRESH_ACT_L 0x21u /* Activity Threshold [5:0] */ 77 #define ADXL367_TIME_ACT 0x22u /* Activity Time */ 78 #define ADXL367_THRESH_INACT_H 0x23u /* Inactivity Threshold [12:6] */ 79 #define ADXL367_THRESH_INACT_L 0x24u /* Inactivity Threshold [5:0] */ 80 #define ADXL367_TIME_INACT_H 0x25u /* Inactivity Time [12:6] */ 81 #define ADXL367_TIME_INACT_L 0x26u /* Inactivity Time [5:0] */ 82 #define ADXL367_ACT_INACT_CTL 0x27u /* Activity Inactivity Control */ 83 #define ADXL367_FIFO_CONTROL 0x28u /* FIFO Control */ 84 #define ADXL367_FIFO_SAMPLES 0x29u /* FIFO Samples */ 85 #define ADXL367_INTMAP1_LOWER 0x2Au /* Interrupt 1 mapping control lower */ 86 #define ADXL367_INTMAP2_LOWER 0x2Bu /* Interrupt 2 mapping control lower */ 87 #define ADXL367_FILTER_CTL 0x2Cu /* Filter Control register */ 88 #define ADXL367_POWER_CTL 0x2Du /* Power Control register */ 89 #define ADXL367_SELF_TEST 0x2Eu /* Self Test */ 90 #define ADXL367_TAP_THRESH 0x2Fu /* Tap Threshold */ 91 #define ADXL367_TAP_DUR 0x30u /* Tap Duration */ 92 #define ADXL367_TAP_LATENT 0x31u /* Tap Latency */ 93 #define ADXL367_TAP_WINDOW 0x32u /* Tap Window */ 94 #define ADXL367_X_OFFSET 0x33u /* X-axis offset */ 95 #define ADXL367_Y_OFFSET 0x34u /* Y-axis offset */ 96 #define ADXL367_Z_OFFSET 0x35u /* Z-axis offset */ 97 #define ADXL367_X_SENS 0x36u /* X-axis user sensitivity */ 98 #define ADXL367_Y_SENS 0x37u /* Y-axis user sensitivity */ 99 #define ADXL367_Z_SENS 0x38u /* Z-axis user sensitivity */ 100 #define ADXL367_TIMER_CTL 0x39u /* Timer Control */ 101 #define ADXL367_INTMAP1_UPPER 0x3Au /* Interrupt 1 mapping control upper */ 102 #define ADXL367_INTMAP2_UPPER 0x3Bu /* Interrupt 2 mapping control upper */ 103 #define ADXL367_ADC_CTL 0x3Cu /* ADC Control Register */ 104 #define ADXL367_TEMP_CTL 0x3Du /* Temperature Control Register */ 105 #define ADXL367_TEMP_ADC_OTH_H 0x3Eu /* Temperature ADC Over Threshold [12:6]*/ 106 #define ADXL367_TEMP_ADC_OTH_L 0x3Fu /* Temperature ADC Over Threshold [5:0]*/ 107 #define ADXL367_TEMP_ADC_UTH_H 0x40u /* Temperature ADC Under Threshold [12:6]*/ 108 #define ADXL367_TEMP_ADC_UTH_L 0x41u /* Temperature ADC Under Threshold [5:0]*/ 109 #define ADXL367_TEMP_ADC_TIMER 0x42u /* Temperature Activiy Inactivity Timer */ 110 #define ADXL367_AXIS_MASK 0x43u /* Axis Mask Register */ 111 #define ADXL367_STATUS_COPY 0x44u /* Status Copy Register */ 112 #define ADXL367_STATUS2 0x45u /* Status 2 Register */ 113 114 #define ADXL367_DEVID_VAL 0xADu /* Analog Devices accelerometer ID */ 115 #define ADXL367_MST_DEVID_VAL 0x1Du /* Analog Devices MEMS device ID */ 116 #define ADXL367_PARTID_VAL 0xF7u /* Device ID */ 117 #define ADXL367_REVID_VAL 0x03u /* product revision ID*/ 118 #define ADXL367_RESET_CODE 0x52u /* Writing code 0x52 resets the device */ 119 120 #define ADXL367_READ 0x01u 121 #define ADXL367_REG_READ(x) (((x & 0xFF) << 1) | ADXL367_READ) 122 #define ADXL367_REG_WRITE(x) ((x & 0xFF) << 1) 123 #define ADXL367_TO_REG(x) ((x) >> 1) 124 #define ADXL367_SPI_WRITE_REG 0x0Au 125 #define ADXL367_SPI_READ_REG 0x0Bu 126 #define ADXL367_SPI_READ_FIFO 0x0Du 127 128 #define ADXL367_ABSOLUTE 0x00 129 #define ADXL367_REFERENCED 0x01 130 131 /* ADXL367_POWER_CTL */ 132 #define ADXL367_POWER_CTL_EXT_CLK_MSK BIT(6) 133 #define ADXL367_POWER_CTL_NOISE_MSK GENMASK(5, 4) 134 #define ADXL367_POWER_CTL_WAKEUP_MSK BIT(3) 135 #define ADXL367_POWER_CTL_AUTOSLEEP_MSK BIT(2) 136 #define ADXL367_POWER_CTL_MEASURE_MSK GENMASK(1, 0) 137 138 /* ADXL367_ACT_INACT_CTL */ 139 #define ADXL367_ACT_INACT_CTL_LINKLOOP_MSK GENMASK(5, 4) 140 #define ADXL367_ACT_INACT_CTL_INACT_REF_MSK BIT(3) 141 #define ADXL367_ACT_INACT_CTL_INACT_EN_MSK BIT(2) 142 #define ADXL367_ACT_INACT_CTL_ACT_REF_MSK BIT(1) 143 #define ADXL367_ACT_INACT_CTL_ACT_EN_MSK BIT(0) 144 145 /* ADXL367_ACT_INACT_CTL_INACT_EN options */ 146 #define ADXL367_NO_INACTIVITY_DETECTION_ENABLED 0x0 147 #define ADXL367_INACTIVITY_ENABLE 0x1 148 #define ADXL367_NO_INACTIVITY_DETECTION_ENABLED_2 0x2 149 #define ADXL367_REFERENCED_INACTIVITY_ENABLE 0x3 150 151 /* ADXL367_ACT_INACT_CTL_ACT_EN options */ 152 #define ADXL367_NO_ACTIVITY_DETECTION 0x0 153 #define ADXL367_ACTIVITY_ENABLE 0x1 154 #define ADXL367_NO_ACTIVITY_DETECTION_2 0x2 155 #define ADXL367_REFERENCED_ACTIVITY_ENABLE 0x3 156 157 #define ADXL367_TEMP_OFFSET 1185 158 #define ADXL367_TEMP_25C 165 159 #define ADXL367_TEMP_SCALE 18518518LL 160 #define ADXL367_TEMP_SCALE_DIV 1000000000 161 162 #define ADXL367_THRESH_H_MSK GENMASK(6, 0) 163 #define ADXL367_THRESH_L_MSK GENMASK(7, 2) 164 165 /* ADXL367_REG_TEMP_CTL definitions. */ 166 #define ADXL367_TEMP_INACT_EN_MSK BIT(3) 167 #define ADXL367_TEMP_ACT_EN_MSK BIT(1) 168 #define ADXL367_TEMP_EN_MSK BIT(0) 169 170 /* ADXL367_SELF_TEST */ 171 #define ADXL367_SELF_TEST_ST_FORCE_MSK BIT(1) 172 #define ADXL367_SELF_TEST_ST_MSK BIT(0) 173 174 /* ADXL367_REG_FILTER_CTL definitions */ 175 #define ADXL367_FILTER_CTL_RANGE_MSK GENMASK(7, 6) 176 #define ADXL367_FILTER_I2C_HS BIT(5) 177 #define ADXL367_FILTER_CTL_RES BIT(4) 178 #define ADXL367_FILTER_CTL_EXT_SAMPLE BIT(3) 179 #define ADXL367_FILTER_CTL_ODR_MSK GENMASK(2, 0) 180 181 /* ADXL367_REG_FIFO_CONTROL */ 182 #define ADXL367_FIFO_CONTROL_FIFO_CHANNEL_MSK GENMASK(6, 3) 183 #define ADXL367_FIFO_CONTROL_FIFO_SAMPLES_MSK BIT(2) 184 #define ADXL367_FIFO_CONTROL_FIFO_MODE_MSK GENMASK(1, 0) 185 186 /* ADXL367_REG_ADC_CTL definitions. */ 187 #define ADXL367_FIFO_8_12BIT_MSK GENMASK(7, 6) 188 #define ADXL367_ADC_INACT_EN BIT(3) 189 #define ADXL367_ADC_ACT_EN BIT(1) 190 #define ADXL367_ADC_EN BIT(0) 191 192 /* ADXL367_REG_STATUS definitions */ 193 #define ADXL367_STATUS_ERR_USER_REGS BIT(7) 194 #define ADXL367_STATUS_AWAKE BIT(6) 195 #define ADXL367_STATUS_INACT BIT(5) 196 #define ADXL367_STATUS_ACT BIT(4) 197 #define ADXL367_STATUS_FIFO_OVERRUN BIT(3) 198 #define ADXL367_STATUS_FIFO_WATERMARK BIT(2) 199 #define ADXL367_STATUS_FIFO_RDY BIT(1) 200 #define ADXL367_STATUS_DATA_RDY BIT(0) 201 202 /* ADXL367_INTMAP_LOWER */ 203 #define ADXL367_INT_LOW BIT(7) 204 #define ADXL367_AWAKE_INT BIT(6) 205 #define ADXL367_INACT_INT BIT(5) 206 #define ADXL367_ACT_INT BIT(4) 207 #define ADXL367_FIFO_OVERRUN BIT(3) 208 #define ADXL367_FIFO_WATERMARK BIT(2) 209 #define ADXL367_FIFO_RDY BIT(1) 210 #define ADXL367_DATA_RDY BIT(0) 211 212 /* ADXL367_INTMAP_UPPER */ 213 #define ADXL367_ERR_FUSE BIT(7) 214 #define ADXL367_ERR_USER_REGS BIT(6) 215 #define ADXL367_KPALV_TIMER BIT(4) 216 #define ADXL367_TEMP_ADC_HI BIT(3) 217 #define ADXL367_TEMP_ADC_LOW BIT(2) 218 #define ADXL367_TAP_TWO BIT(1) 219 #define ADXL367_TAP_ONE BIT(0) 220 221 /* Min change = 90mg. Sensitivity = 4LSB / mg */ 222 #define ADXL367_SELF_TEST_MIN (90 * 100 / 25) 223 /* Max change = 270mg. Sensitivity = 4LSB / mg */ 224 #define ADXL367_SELF_TEST_MAX (270 * 100 / 25) 225 226 /* ADXL367 get fifo sample header */ 227 #define ADXL367_FIFO_HDR_GET_ACCEL_AXIS(x) (((x) & 0xC000) >> 14) 228 #define ADXL367_FIFO_HDR_CHECK_TEMP(x) ((((x) & 0xC000) >> 14) == 0x3) 229 230 /* ADXL362 scale factors from specifications */ 231 #define ADXL367_ACCEL_2G_LSB_PER_G 4000 232 #define ADXL367_ACCEL_4G_LSB_PER_G 2000 233 #define ADXL367_ACCEL_8G_LSB_PER_G 1000 234 235 enum adxl367_axis { 236 ADXL367_X_AXIS = 0x0, 237 ADXL367_Y_AXIS = 0x1, 238 ADXL367_Z_AXIS = 0x2 239 }; 240 241 enum adxl367_op_mode { 242 ADXL367_STANDBY = 0, 243 ADXL367_MEASURE = 2, 244 }; 245 246 enum adxl367_range { 247 ADXL367_2G_RANGE, 248 ADXL367_4G_RANGE, 249 ADXL367_8G_RANGE, 250 }; 251 252 enum adxl367_act_proc_mode { 253 ADXL367_DEFAULT = 0, 254 ADXL367_LINKED = 1, 255 ADXL367_LOOPED = 3, 256 }; 257 258 enum adxl367_odr { 259 ADXL367_ODR_12P5HZ, 260 ADXL367_ODR_25HZ, 261 ADXL367_ODR_50HZ, 262 ADXL367_ODR_100HZ, 263 ADXL367_ODR_200HZ, 264 ADXL367_ODR_400HZ, 265 }; 266 267 enum adxl367_fifo_format { 268 ADXL367_FIFO_FORMAT_XYZ, 269 ADXL367_FIFO_FORMAT_X, 270 ADXL367_FIFO_FORMAT_Y, 271 ADXL367_FIFO_FORMAT_Z, 272 ADXL367_FIFO_FORMAT_XYZT, 273 ADXL367_FIFO_FORMAT_XT, 274 ADXL367_FIFO_FORMAT_YT, 275 ADXL367_FIFO_FORMAT_ZT, 276 ADXL367_FIFO_FORMAT_XYZA, 277 ADXL367_FIFO_FORMAT_XA, 278 ADXL367_FIFO_FORMAT_YA, 279 ADXL367_FIFO_FORMAT_ZA 280 }; 281 282 enum adxl367_fifo_mode { 283 ADXL367_FIFO_DISABLED, 284 ADXL367_OLDEST_SAVED, 285 ADXL367_STREAM_MODE, 286 ADXL367_TRIGGERED_MODE 287 }; 288 289 enum adxl367_fifo_read_mode { 290 ADXL367_12B_CHID, 291 ADXL367_8B, 292 ADXL367_12B, 293 ADXL367_14B_CHID 294 }; 295 296 struct adxl367_fifo_config { 297 enum adxl367_fifo_mode fifo_mode; 298 enum adxl367_fifo_format fifo_format; 299 enum adxl367_fifo_read_mode fifo_read_mode; 300 uint16_t fifo_samples; 301 }; 302 303 struct adxl367_activity_threshold { 304 uint16_t value; 305 bool referenced; 306 bool enable; 307 }; 308 309 struct adxl367_xyz_accel_data { 310 int16_t x; 311 int16_t y; 312 int16_t z; 313 enum adxl367_range range; 314 }; 315 316 struct adxl367_sample_data { 317 #ifdef CONFIG_ADXL367_STREAM 318 uint8_t is_fifo: 1; 319 uint8_t res: 7; 320 #endif /*CONFIG_ADXL367_STREAM*/ 321 struct adxl367_xyz_accel_data xyz; 322 int16_t raw_temp; 323 }; 324 325 struct adxl367_transfer_function { 326 int (*read_reg_multiple)(const struct device *dev, uint8_t reg_addr, 327 uint8_t *value, uint16_t len); 328 int (*write_reg)(const struct device *dev, uint8_t reg_addr, 329 uint8_t value); 330 int (*read_reg)(const struct device *dev, uint8_t reg_addr, 331 uint8_t *value); 332 int (*write_reg_mask)(const struct device *dev, uint8_t reg_addr, 333 uint32_t mask, uint8_t value); 334 }; 335 336 struct adxl367_data { 337 struct adxl367_xyz_accel_data sample; 338 int16_t temp_val; 339 const struct adxl367_transfer_function *hw_tf; 340 struct adxl367_fifo_config fifo_config; 341 enum adxl367_act_proc_mode act_proc_mode; 342 enum adxl367_range range; 343 #ifdef CONFIG_ADXL367_TRIGGER 344 struct gpio_callback gpio_cb; 345 346 sensor_trigger_handler_t th_handler; 347 const struct sensor_trigger *th_trigger; 348 sensor_trigger_handler_t drdy_handler; 349 const struct sensor_trigger *drdy_trigger; 350 const struct device *dev; 351 352 #if defined(CONFIG_ADXL367_TRIGGER_OWN_THREAD) 353 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL367_THREAD_STACK_SIZE); 354 struct k_sem gpio_sem; 355 struct k_thread thread; 356 #elif defined(CONFIG_ADXL367_TRIGGER_GLOBAL_THREAD) 357 struct k_work work; 358 #endif 359 #endif /* CONFIG_ADXL367_TRIGGER */ 360 #ifdef CONFIG_ADXL367_STREAM 361 uint8_t status; 362 uint8_t fifo_ent[2]; 363 struct rtio_iodev_sqe *sqe; 364 struct rtio *rtio_ctx; 365 struct rtio_iodev *iodev; 366 uint64_t timestamp; 367 struct rtio *r_cb; 368 uint8_t fifo_full_irq: 1; 369 uint8_t fifo_wmark_irq: 1; 370 uint8_t res: 6; 371 enum adxl367_odr odr; 372 uint8_t pwr_reg; 373 #endif /* CONFIG_ADXL367_STREAM */ 374 }; 375 376 struct adxl367_dev_config { 377 #ifdef ADXL367_BUS_I2C 378 struct i2c_dt_spec i2c; 379 #endif /* ADXL367_BUS_I2C */ 380 #ifdef ADXL367_BUS_SPI 381 struct spi_dt_spec spi; 382 #endif /* ADXL367_BUS_SPI */ 383 int (*bus_init)(const struct device *dev); 384 385 #ifdef CONFIG_ADXL367_TRIGGER 386 struct gpio_dt_spec interrupt; 387 #endif 388 389 enum adxl367_odr odr; 390 391 /* Device Settings */ 392 bool autosleep; 393 bool low_noise; 394 bool temp_en; 395 396 struct adxl367_activity_threshold activity_th; 397 struct adxl367_activity_threshold inactivity_th; 398 struct adxl367_fifo_config fifo_config; 399 400 enum adxl367_range range; 401 enum adxl367_op_mode op_mode; 402 403 uint16_t inactivity_time; 404 uint8_t activity_time; 405 uint8_t chip_id; 406 }; 407 408 struct adxl367_fifo_data { 409 uint8_t is_fifo: 1; 410 uint8_t res: 7; 411 uint8_t packet_size; 412 uint8_t fifo_read_mode; 413 uint8_t has_tmp: 1; 414 uint8_t has_adc: 1; 415 uint8_t has_x: 1; 416 uint8_t has_y: 1; 417 uint8_t has_z: 1; 418 uint8_t res1: 3; 419 uint8_t int_status; 420 uint8_t accel_odr: 4; 421 uint8_t range: 4; 422 uint16_t fifo_byte_count; 423 uint64_t timestamp; 424 } __attribute__((__packed__)); 425 426 BUILD_ASSERT(sizeof(struct adxl367_fifo_data) % 4 == 0, 427 "adxl367_fifo_data struct should be word aligned"); 428 429 int adxl367_spi_init(const struct device *dev); 430 int adxl367_i2c_init(const struct device *dev); 431 int adxl367_trigger_set(const struct device *dev, 432 const struct sensor_trigger *trig, 433 sensor_trigger_handler_t handler); 434 435 int adxl367_init_interrupt(const struct device *dev); 436 void adxl367_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 437 void adxl367_stream_irq_handler(const struct device *dev); 438 439 #ifdef CONFIG_SENSOR_ASYNC_API 440 void adxl367_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); 441 int adxl367_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); 442 int adxl367_get_accel_data(const struct device *dev, 443 struct adxl367_xyz_accel_data *accel_data); 444 int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp); 445 void adxl367_accel_convert(struct sensor_value *val, int16_t value, 446 enum adxl367_range range); 447 void adxl367_temp_convert(struct sensor_value *val, int16_t value); 448 #endif /* CONFIG_SENSOR_ASYNC_API */ 449 450 #ifdef CONFIG_ADXL367_STREAM 451 int adxl367_fifo_setup(const struct device *dev, 452 enum adxl367_fifo_mode mode, 453 enum adxl367_fifo_format format, 454 enum adxl367_fifo_read_mode read_mode, 455 uint8_t sets_nb); 456 int adxl367_set_op_mode(const struct device *dev, 457 enum adxl367_op_mode op_mode); 458 size_t adxl367_get_packet_size(const struct adxl367_dev_config *cfg); 459 #endif /* CONFIG_ADXL367_STREAM */ 460 461 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ */ 462
