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Searched refs:pllm_reg (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_agilex_ll.c57 uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; in get_clk_freq() local
63 pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM; in get_clk_freq()
68 pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM; in get_clk_freq()
77 mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg)); in get_clk_freq()
Dclock_control_agilex5_ll.c85 uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; in get_clk_freq() local
91 pllm_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLM; in get_clk_freq()
97 pllm_reg = clock_agilex5_ll.peripll_addr + CLKMGR_PERPLL_PLLM; in get_clk_freq()
107 mdiv = CLKMGR_PLLM_MDIV(sys_read32(pllm_reg)); in get_clk_freq()