| /Zephyr-Core-3.6.0/samples/modules/tflite-micro/magic_wand/src/ |
| D | output_handler.cpp | 19 void HandleOutput(int kind) in HandleOutput() argument
22 if (kind == 0) { in HandleOutput()
27 } else if (kind == 1) { in HandleOutput()
32 } else if (kind == 2) { in HandleOutput()
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| D | output_handler.hpp | 23 void HandleOutput(int kind);
|
| /Zephyr-Core-3.6.0/scripts/build/ |
| D | gen_relocate_app.py | 312 for kind in SectionKind:
315 out.add(kind)
336 kind: SectionKind,
351 if full_list_of_sections[kind]:
354 tmp = print_linker_sections(full_list_of_sections[kind])
355 if region_is_default_ram(memory_type) and kind in (SectionKind.DATA, SectionKind.BSS):
358 if not region_is_default_ram(memory_type) and kind is SectionKind.RODATA:
363 …linker_string += LINKER_SECTION_SEQ_MPU.format(memory_type.lower(), kind.value, memory_type.upper(…
364 … kind, tmp, load_address_string, align_size)
366 … if region_is_default_ram(memory_type) and kind in (SectionKind.TEXT, SectionKind.LITERAL):
[all …]
|
| /Zephyr-Core-3.6.0/tests/net/lib/lwm2m/interop/pytest/ |
| D | leshan.py | 105 kind = 'singleResource'
107 kind = 'resourceInstance'
109 return self.put(f'/clients/{endpoint}/{path}', self._define_resource(rid, value, kind))
179 kind = 'multiResource'
181 kind = 'singleResource'
182 data['resources'].append(cls._define_resource(key, value, kind))
186 def _define_resource(cls, rid, value, kind='singleResource'): argument
188 if kind in ('singleResource', 'resourceInstance'):
191 "kind": kind,
195 if kind == 'multiResource':
[all …]
|
| /Zephyr-Core-3.6.0/boards/arc/nsim/support/ |
| D | mdb_hs_flash_xip.args | 37 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | mdb_hs_sram.args | 37 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | nsim_hs_flash_xip.props | 41 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | nsim_hs_sram.props | 41 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_hs6x.args | 51 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_hs.args | 44 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_hs_mpuv6.args | 44 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | nsim_hs.props | 48 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_hs5x.args | 51 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | nsim_hs_mpuv6.props | 48 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | mdb_hs_smp.args | 48 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=0,use_connect=1
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| D | nsim_em7d_v22.props | 57 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | mdb_em7d_v22.args | 52 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | nsim_hs5x.props | 60 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | nsim_hs6x.props | 59 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | mdb_hs6x_smp.args | 63 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_hs6x_smp_12cores.args | 63 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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| D | mdb_hs5x_smp.args | 64 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_hs5x_smp_12cores.args | 64 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | mdb_sem.args | 58 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
| D | nsim_sem.props | 63 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
|
