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Searched refs:pcc (Results 1 – 15 of 15) sorted by relevance

/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dsoc_clock.h20 #define NPCX_CLK_CTRL_NODE DT_NODELABEL(pcc)
36 #define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
46 #if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
56 #define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \
78 #define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
/Zephyr-Core-3.5.0/dts/arm/nuvoton/
Dm46x.dtsi52 pcc: peripheral-clock-controller { label
53 compatible = "nuvoton,numaker-pcc";
84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC
94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC
104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC
114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC
124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC
134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC
144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC
154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/
Dnpcx.dtsi90 pcc: clock-controller@4000d000 { label
91 compatible = "nuvoton,npcx-pcc";
279 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>;
288 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>;
297 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>;
306 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>;
315 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>;
324 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>;
333 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>;
342 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>;
[all …]
Dnpcx4.dtsi70 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
71 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
79 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4>;
88 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
97 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4>;
106 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3>;
112 pcc: clock-controller@4000d000 { label
271 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>;
280 clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 5>;
289 clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 6>;
Dnpcx9.dtsi69 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
70 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
78 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4>;
87 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
96 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4>;
105 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3>;
111 pcc: clock-controller@4000d000 { label
266 clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
Dnpcx7.dtsi68 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 3
69 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
77 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
86 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 6>;
92 pcc: clock-controller@4000d000 { label
245 clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_ke1xf.dtsi260 pcc: pcc@40065000 { label
261 compatible = "nxp,kinetis-pcc";
330 clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>;
341 clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>;
352 clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>;
365 clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>;
376 clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>;
384 clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>;
394 clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>;
427 clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
[all …]
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_numaker_scc.c33 CLK_EnableModuleClock(scc_subsys->pcc.clk_modidx); in numaker_scc_on()
50 CLK_DisableModuleClock(scc_subsys->pcc.clk_modidx); in numaker_scc_off()
87 CLK_SetModuleClock(scc_subsys->pcc.clk_modidx, scc_subsys->pcc.clk_src, in numaker_scc_configure()
88 scc_subsys->pcc.clk_div); in numaker_scc_configure()
/Zephyr-Core-3.5.0/include/zephyr/drivers/clock_control/
Dclock_control_numaker.h37 } pcc; member
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_numaker.c288 scc_subsys.pcc.clk_modidx = dev_cfg->clk_modidx; in spi_numaker_init()
289 scc_subsys.pcc.clk_src = dev_cfg->clk_src; in spi_numaker_init()
290 scc_subsys.pcc.clk_div = dev_cfg->clk_div; in spi_numaker_init()
/Zephyr-Core-3.5.0/drivers/serial/
Duart_numaker.c199 scc_subsys.pcc.clk_modidx = config->clk_modidx; in uart_numaker_init()
200 scc_subsys.pcc.clk_src = config->clk_src; in uart_numaker_init()
201 scc_subsys.pcc.clk_div = config->clk_div; in uart_numaker_init()
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_numaker.c481 scc_subsys.pcc.clk_modidx = cfg->clk_modidx; in pwm_numaker_init()
482 scc_subsys.pcc.clk_src = cfg->clk_src; in pwm_numaker_init()
483 scc_subsys.pcc.clk_div = cfg->clk_div; in pwm_numaker_init()
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_numaker.c62 scc_subsys.pcc.clk_modidx = config->clk_modidx; in gpio_numaker_configure()
/Zephyr-Core-3.5.0/dts/riscv/openisa/
Drv32m1.dtsi61 compatible = "openisa,rv32m1-pcc";
67 compatible = "openisa,rv32m1-pcc";
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.5.rst1518 * :dtcompatible:`nuvoton,numaker-pcc`
1546 * :dtcompatible:`nuvoton,npcx-pcc`: