Searched refs:dw_read (Results 1 – 4 of 4) sorted by relevance
/Zephyr-Core-3.5.0/drivers/dma/ |
D | dma_intel_adsp_gpdma.c | 64 cap = dw_read(dev_cfg->shim, 0x0); in intel_adsp_gpdma_dump_registers() 65 ctl = dw_read(dev_cfg->shim, 0x4); in intel_adsp_gpdma_dump_registers() 66 ipptr = dw_read(dev_cfg->shim, 0x8); in intel_adsp_gpdma_dump_registers() 67 llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_dump_registers() 68 llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel)); in intel_adsp_gpdma_dump_registers() 69 llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel)); in intel_adsp_gpdma_dump_registers() 77 dw_read(dw_cfg->base, DW_CHAN_OFFSET(channel) + chan_reg_offs[i])); in intel_adsp_gpdma_dump_registers() 83 dw_read(dw_cfg->base, ip_reg_offs[i])); in intel_adsp_gpdma_dump_registers() 105 val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_llp_enable() 120 val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel)); in intel_adsp_gpdma_llp_disable() [all …]
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D | dma_dw_common.c | 38 status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS); in dw_dma_isr() 44 status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK); in dw_dma_isr() 45 status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR); in dw_dma_isr() 48 status_err = dw_read(dev_cfg->base, DW_STATUS_ERR); in dw_dma_isr() 437 return dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN_MASK(channel); in dw_dma_is_enabled() 462 dw_read(dev_cfg->base, DW_DMA_CHAN_EN), in dw_dma_start() 490 lli->ctrl_lo, masked_ctrl_lo, dw_read(dev_cfg->base, DW_LLP(channel))); in dw_dma_start() 515 chan_data->cfg_hi, dw_read(dev_cfg->base, DW_LLP(channel)) in dw_dma_start() 520 chan_data->cfg_hi, dw_read(dev_cfg->base, DW_LLP(channel)) in dw_dma_start() 583 bool fifo_empty = WAIT_FOR(dw_read(dev_cfg->base, DW_CFG_LOW(channel)) & DW_CFGL_FIFO_EMPTY, in dw_dma_stop() [all …]
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D | dma_dw_common.h | 266 static ALWAYS_INLINE uint32_t dw_read(uintptr_t dma_base, uint32_t reg) in dw_read() function
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/Zephyr-Core-3.5.0/drivers/gpio/ |
D | gpio_dw.c | 38 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() function 59 static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset) in dw_read() function 199 dir_reg = dw_read(base_addr, dir_port) & BIT(pin); in gpio_dw_pin_interrupt_configure() 311 *value = dw_read(base_addr, ext_port); in gpio_dw_port_get_raw() 325 pins = dw_read(base_addr, data_port); in gpio_dw_port_set_masked_raw() 340 pins = dw_read(base_addr, data_port); in gpio_dw_port_set_bits_raw() 356 pins = dw_read(base_addr, data_port); in gpio_dw_port_clear_bits_raw() 371 pins = dw_read(base_addr, data_port); in gpio_dw_port_toggle_bits() 393 int_status = dw_read(base_addr, INTSTATUS); in gpio_dw_isr()
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