Home
last modified time | relevance | path

Searched refs:adc (Results 1 – 25 of 505) sorted by relevance

12345678910>>...21

/Zephyr-Core-3.5.0/drivers/adc/
DKconfig53 source "drivers/adc/Kconfig.b91"
55 source "drivers/adc/Kconfig.it8xxx2"
57 source "drivers/adc/Kconfig.mcux"
59 source "drivers/adc/Kconfig.nrfx"
61 source "drivers/adc/Kconfig.sam_afec"
63 source "drivers/adc/Kconfig.sam"
65 source "drivers/adc/Kconfig.sam0"
67 source "drivers/adc/Kconfig.stm32"
69 source "drivers/adc/Kconfig.esp32"
71 source "drivers/adc/Kconfig.xec"
[all …]
Dadc_shell.c125 struct adc_hdl *adc = get_adc(argv[-2]); in cmd_adc_ch_id() local
128 if (!device_is_ready(adc->dev)) { in cmd_adc_ch_id()
138 adc->channel_config.channel_id = (uint8_t)strtol(argv[1], NULL, 10); in cmd_adc_ch_id()
139 retval = adc_channel_setup(adc->dev, &adc->channel_config); in cmd_adc_ch_id()
148 struct adc_hdl *adc = get_adc(argv[-2]); in cmd_adc_ch_diff() local
153 if (!device_is_ready(adc->dev)) { in cmd_adc_ch_diff()
165 adc->channel_config.differential = (uint8_t)diff; in cmd_adc_ch_diff()
166 retval = adc_channel_setup(adc->dev, &adc->channel_config); in cmd_adc_ch_diff()
176 struct adc_hdl *adc = get_adc(argv[-2]); in cmd_adc_ch_neg() local
179 if (!device_is_ready(adc->dev)) { in cmd_adc_ch_neg()
[all …]
Dadc_stm32.c222 ADC_TypeDef *adc = (ADC_TypeDef *)config->base; in adc_stm32_dma_start() local
235 blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA); in adc_stm32_dma_start()
263 if (adc == ADC3) { in adc_stm32_dma_start()
264 LL_ADC_REG_SetDMATransferMode(adc, in adc_stm32_dma_start()
266 LL_ADC_EnableDMAReq(adc); in adc_stm32_dma_start()
268 LL_ADC_REG_SetDataTransferMode(adc, in adc_stm32_dma_start()
272 LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); in adc_stm32_dma_start()
347 ADC_TypeDef *adc = (ADC_TypeDef *)config->base; in adc_stm32_start_conversion() local
353 LL_ADC_REG_StartConversion(adc); in adc_stm32_start_conversion()
355 LL_ADC_REG_StartConversionSWStart(adc); in adc_stm32_start_conversion()
[all …]
Dadc_sam0.c64 static void wait_synchronization(Adc *const adc) in wait_synchronization() argument
66 while ((ADC_SYNC(adc) & ADC_SYNC_MASK) != 0) { in wait_synchronization()
119 Adc *const adc = cfg->regs; in adc_sam0_channel_setup() local
134 adc->SAMPCTRL.reg = sampctrl; in adc_sam0_channel_setup()
135 wait_synchronization(adc); in adc_sam0_channel_setup()
165 if (adc->REFCTRL.reg != refctrl) { in adc_sam0_channel_setup()
167 adc->CTRLA.bit.ENABLE = 0; in adc_sam0_channel_setup()
168 wait_synchronization(adc); in adc_sam0_channel_setup()
170 adc->REFCTRL.reg = refctrl; in adc_sam0_channel_setup()
171 wait_synchronization(adc); in adc_sam0_channel_setup()
[all …]
Dadc_sam.c70 Adc *const adc = cfg->regs; in adc_sam_channel_setup() local
99 adc->ADC_ACR |= ADC_ACR_TSON; in adc_sam_channel_setup()
104 adc->ADC_COR |= (ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U); in adc_sam_channel_setup()
106 adc->ADC_COR &= ~((ADC_COR_DIFF0 | ADC_COR_DIFF1) << (channel_id * 2U)); in adc_sam_channel_setup()
110 adc->ADC_CGR &= ~(ADC_CGR_GAIN0_Msk << (channel_id * 2U)); in adc_sam_channel_setup()
121 adc->ADC_CGR |= ADC_CGR_GAIN0(1) << (channel_id * 2U); in adc_sam_channel_setup()
124 adc->ADC_CGR |= ADC_CGR_GAIN0(2) << (channel_id * 2U); in adc_sam_channel_setup()
131 adc->ADC_CGR |= ADC_CGR_GAIN0(3) << (channel_id * 2U); in adc_sam_channel_setup()
144 Adc *const adc = cfg->regs; in adc_sam_start_conversion() local
146 adc->ADC_CR = ADC_CR_START; in adc_sam_start_conversion()
[all …]
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/
Dadc_fixup_sam0.h11 #define ADC_SYNC(adc) ((adc)->SYNCBUSY.reg) argument
14 #define ADC_SYNC(adc) ((adc)->STATUS.reg) argument
21 #define ADC_DIFF(adc) (inputctrl) argument
24 #define ADC_DIFF(adc) ((adc)->CTRLB.reg) argument
27 #define ADC_DIFF(adc) ((adc)->CTRLC.reg) argument
34 #define ADC_RESSEL(adc) ((adc)->CTRLB.bit.RESSEL) argument
40 #define ADC_RESSEL(adc) ((adc)->CTRLC.bit.RESSEL) argument
50 #define ADC_PRESCALER(adc) ((adc)->CTRLA.bit.PRESCALER) argument
53 #define ADC_PRESCALER(adc) ((adc)->CTRLB.bit.PRESCALER) argument
/Zephyr-Core-3.5.0/boards/arm/actinius_icarus_som_dk/
Darduino_connector.dtsi38 compatible = "arduino,uno-adc";
40 io-channel-map = <0 &adc 2>, /* A0 = P0.15 = AIN2 */
41 <1 &adc 3>, /* A1 = P0.16 = AIN3 */
42 <2 &adc 4>, /* A2 = P0.17 = AIN4 */
43 <3 &adc 5>, /* A3 = P0.18 = AIN5 */
44 <4 &adc 6>, /* A4 = P0.19 = AIN6 */
45 <5 &adc 7>; /* A5 = P0.20 = AIN7 */
/Zephyr-Core-3.5.0/tests/drivers/regulator/voltage/boards/
Dnrf52840dk_nrf52840_npm6001.overlay16 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
20 adc-avg-count = <10>;
24 &adc {
/Zephyr-Core-3.5.0/drivers/sensor/nuvoton_adc_cmp_npcx/
Dadc_cmp_npcx.c31 const struct device *adc; member
75 ret = adc_npcx_threshold_ctrl_set_param(config->adc, config->th_sel, in adc_cmp_npcx_init()
85 ret = adc_npcx_threshold_ctrl_set_param(config->adc, config->th_sel, in adc_cmp_npcx_init()
95 ret = adc_npcx_threshold_mv_to_thrval(config->adc, config->thr_mv, in adc_cmp_npcx_init()
101 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_init()
116 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_init()
138 ret = adc_npcx_threshold_mv_to_thrval(config->adc, value, &param.val); in adc_cmp_npcx_set_threshold()
144 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_set_threshold()
154 ret = adc_npcx_threshold_ctrl_set_param(config->adc, in adc_cmp_npcx_set_threshold()
190 ret = adc_npcx_threshold_ctrl_enable(config->adc, in adc_cmp_npcx_attr_set()
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/stm32_vbat/
Dstm32_vbat.c23 const struct device *adc; member
48 rc = adc_channel_setup(data->adc, &data->adc_cfg); in stm32_vbat_sample_fetch()
58 rc = adc_read(data->adc, sp); in stm32_vbat_sample_fetch()
81 voltage = data->raw * adc_ref_internal(data->adc) / 0x0FFF; in stm32_vbat_channel_get()
100 if (!device_is_ready(data->adc)) { in stm32_vbat_init()
101 LOG_ERR("Device %s is not ready", data->adc->name); in stm32_vbat_init()
117 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst)), \
/Zephyr-Core-3.5.0/drivers/sensor/rpi_pico_temp/
Drpi_pico_temp.c20 const struct device *adc; member
41 rc = adc_channel_setup(cfg->adc, &cfg->ch_cfg); in rpi_pico_temp_sample_fetch()
47 rc = adc_read(cfg->adc, &data->adc_seq); in rpi_pico_temp_sample_fetch()
66 rc = adc_raw_to_millivolts(adc_ref_internal(cfg->adc), cfg->ch_cfg.gain, in rpi_pico_temp_channel_get()
94 if (!device_is_ready(cfg->adc)) { in rpi_pico_temp_init()
95 LOG_ERR("Device %s is not ready", cfg->adc->name); in rpi_pico_temp_init()
106 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst)), \
/Zephyr-Core-3.5.0/drivers/sensor/mcp970x/
Dmcp970x.c30 struct adc_dt_spec adc; member
49 ret = adc_read_dt(&config->adc, &data->sequence); in fetch()
71 ret = adc_raw_to_millivolts_dt(&config->adc, &raw_val); in get()
105 if (!adc_is_ready_dt(&config->adc)) { in init()
110 ret = adc_channel_setup_dt(&config->adc); in init()
116 ret = adc_sequence_init_dt(&config->adc, &data->sequence); in init()
132 .adc = ADC_DT_SPEC_INST_GET(inst), \
/Zephyr-Core-3.5.0/drivers/sensor/grove/
Dlight_sensor.c32 const struct device *adc; member
38 const struct device *adc; member
56 return adc_read(cfg->adc, &adc_table); in gls_sample_fetch()
91 if (!device_is_ready(cfg->adc)) { in gls_init()
111 adc_channel_setup(cfg->adc, &drv_data->ch_cfg); in gls_init()
120 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst)), \
/Zephyr-Core-3.5.0/samples/drivers/adc/boards/
Dnrf52840dk_nrf52840.overlay10 io-channels = <&adc 0>, <&adc 1>, <&adc 7>;
14 &adc {
Dda1469x_dk_pro.overlay7 #include <zephyr/dt-bindings/adc/adc.h>
12 io-channels = <&adc 0 &adc 1 &adc 2 &adc 3 &sdadc 0 &sdadc 1 &sdadc 2>;
33 &adc {
/Zephyr-Core-3.5.0/tests/drivers/adc/adc_api/boards/
Drpi_pico_w.overlay9 io-channels = <&adc 0>, <&adc 1>;
13 &adc {
Drpi_pico.overlay9 io-channels = <&adc 0>, <&adc 1>;
13 &adc {
Dsparkfun_pro_micro_rp2040.overlay9 io-channels = <&adc 0>, <&adc 1>;
13 &adc {
Dadafruit_kb2040.overlay9 io-channels = <&adc 0>, <&adc 1>;
13 &adc {
Dnrf51dk_nrf51422.overlay9 io-channels = <&adc 0>, <&adc 2>;
13 &adc {
Dnordic,nrf-saadc-common.dtsi9 io-channels = <&adc 0>, <&adc 2>;
13 &adc {
/Zephyr-Core-3.5.0/drivers/sensor/stm32_temp/
Dstm32_temp.c37 const struct device *adc; member
77 rc = adc_channel_setup(data->adc, &data->adc_cfg); in stm32_temp_sample_fetch()
87 rc = adc_read(data->adc, sp); in stm32_temp_sample_fetch()
115 temp = ((float)data->raw * adc_ref_internal(data->adc)) / cfg->cal_vrefanalog; in stm32_temp_channel_get()
134 int32_t mv = data->raw * adc_ref_internal(data->adc) / 0x0FFF; in stm32_temp_channel_get()
160 if (!device_is_ready(data->adc)) { in stm32_temp_init()
161 LOG_ERR("Device %s is not ready", data->adc->name); in stm32_temp_init()
176 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(0)),
/Zephyr-Core-3.5.0/samples/boards/nrf/battery/src/
Dbattery.c69 const struct device *adc; member
76 .adc = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(VBATT)),
78 .adc = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(ZEPHYR_USER)),
92 if (!device_is_ready(ddp->adc)) { in divider_setup()
93 LOG_ERR("ADC device is not ready %s", ddp->adc->name); in divider_setup()
137 rc = adc_channel_setup(ddp->adc, accp); in divider_setup()
180 rc = adc_read(ddp->adc, sp); in battery_sample()
185 adc_raw_to_millivolts(adc_ref_internal(ddp->adc), in battery_sample()
/Zephyr-Core-3.5.0/drivers/sensor/stm32_vref/
Dstm32_vref.c22 const struct device *adc; member
48 rc = adc_channel_setup(data->adc, &data->adc_cfg); in stm32_vref_sample_fetch()
60 rc = adc_read(data->adc, sp); in stm32_vref_sample_fetch()
129 if (!device_is_ready(data->adc)) { in stm32_vref_init()
130 LOG_ERR("Device %s is not ready", data->adc->name); in stm32_vref_init()
145 .adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(0)),
/Zephyr-Core-3.5.0/dts/arm/st/f3/
Dstm32f334.dtsi8 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
31 adc1: adc@50000000 {
32 compatible = "st,stm32-adc";
43 st,adc-sequencer = <FULLY_CONFIGURABLE>;

12345678910>>...21