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Searched refs:S_MSC_COMBINED_IRQn (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.5.0/soc/arm/arm/musca_s1/
Dsystem_cmsdk_musca_s1.h47S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt … enumerator
/Zephyr-Core-3.5.0/soc/arm/arm/musca_b1/
Dsystem_cmsdk_musca_b1.h47S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt … enumerator