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Searched refs:MIO_PIN_L1_SEL_MASK (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h37 #define MIO_PIN_L1_SEL_MASK BIT(2) macro
38 #define MIO_PIN_L1_SEL(val) FIELD_PREP(MIO_PIN_L1_SEL_MASK, val)
48 (MIO_PIN_L3_SEL_MASK | MIO_PIN_L2_SEL_MASK | MIO_PIN_L1_SEL_MASK | MIO_PIN_L0_SEL_MASK)