1 /*
2 * Copyright (c) 2022 Vestas Wind Systems A/S
3 * Copyright (c) 2020 Alexander Wachter
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/sys/__assert.h>
15 #include <soc.h>
16 #include <stm32_ll_rcc.h>
17 #include <zephyr/logging/log.h>
18 #include <zephyr/irq.h>
19
20 LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
21
22 #define DT_DRV_COMPAT st_stm32_fdcan
23
24 /*
25 * The STMicroelectronics STM32 FDCAN definitions correspond to those found in the
26 * STMicroelectronics STM32G4 Series Reference manual (RM0440), Rev 7.
27 *
28 * This controller uses a Bosch M_CAN like register layout, but some registers are unimplemented,
29 * some registers are mapped to other register offsets, and some registers have had their bit fields
30 * remapped.
31 *
32 * Apart from the definitions below please note the following limitations:
33 * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34 * - CCCR register VMM and UTSU bits are not available.
35 * - TXBC register TFQS, NDTB, and TBSA fields are not available.
36 */
37
38 /* Interrupt register */
39 #define CAN_STM32FD_IR_ARA BIT(23)
40 #define CAN_STM32FD_IR_PED BIT(22)
41 #define CAN_STM32FD_IR_PEA BIT(21)
42 #define CAN_STM32FD_IR_WDI BIT(20)
43 #define CAN_STM32FD_IR_BO BIT(19)
44 #define CAN_STM32FD_IR_EW BIT(18)
45 #define CAN_STM32FD_IR_EP BIT(17)
46 #define CAN_STM32FD_IR_ELO BIT(16)
47 #define CAN_STM32FD_IR_TOO BIT(15)
48 #define CAN_STM32FD_IR_MRAF BIT(14)
49 #define CAN_STM32FD_IR_TSW BIT(13)
50 #define CAN_STM32FD_IR_TEFL BIT(12)
51 #define CAN_STM32FD_IR_TEFF BIT(11)
52 #define CAN_STM32FD_IR_TEFN BIT(10)
53 #define CAN_STM32FD_IR_TFE BIT(9)
54 #define CAN_STM32FD_IR_TCF BIT(8)
55 #define CAN_STM32FD_IR_TC BIT(7)
56 #define CAN_STM32FD_IR_HPM BIT(6)
57 #define CAN_STM32FD_IR_RF1L BIT(5)
58 #define CAN_STM32FD_IR_RF1F BIT(4)
59 #define CAN_STM32FD_IR_RF1N BIT(3)
60 #define CAN_STM32FD_IR_RF0L BIT(2)
61 #define CAN_STM32FD_IR_RF0F BIT(1)
62 #define CAN_STM32FD_IR_RF0N BIT(0)
63
64 /* Interrupt Enable register */
65 #define CAN_STM32FD_IE_ARAE BIT(23)
66 #define CAN_STM32FD_IE_PEDE BIT(22)
67 #define CAN_STM32FD_IE_PEAE BIT(21)
68 #define CAN_STM32FD_IE_WDIE BIT(20)
69 #define CAN_STM32FD_IE_BOE BIT(19)
70 #define CAN_STM32FD_IE_EWE BIT(18)
71 #define CAN_STM32FD_IE_EPE BIT(17)
72 #define CAN_STM32FD_IE_ELOE BIT(16)
73 #define CAN_STM32FD_IE_TOOE BIT(15)
74 #define CAN_STM32FD_IE_MRAFE BIT(14)
75 #define CAN_STM32FD_IE_TSWE BIT(13)
76 #define CAN_STM32FD_IE_TEFLE BIT(12)
77 #define CAN_STM32FD_IE_TEFFE BIT(11)
78 #define CAN_STM32FD_IE_TEFNE BIT(10)
79 #define CAN_STM32FD_IE_TFEE BIT(9)
80 #define CAN_STM32FD_IE_TCFE BIT(8)
81 #define CAN_STM32FD_IE_TCE BIT(7)
82 #define CAN_STM32FD_IE_HPME BIT(6)
83 #define CAN_STM32FD_IE_RF1LE BIT(5)
84 #define CAN_STM32FD_IE_RF1FE BIT(4)
85 #define CAN_STM32FD_IE_RF1NE BIT(3)
86 #define CAN_STM32FD_IE_RF0LE BIT(2)
87 #define CAN_STM32FD_IE_RF0FE BIT(1)
88 #define CAN_STM32FD_IE_RF0NE BIT(0)
89
90 /* Interrupt Line Select register */
91 #define CAN_STM32FD_ILS_PERR BIT(6)
92 #define CAN_STM32FD_ILS_BERR BIT(5)
93 #define CAN_STM32FD_ILS_MISC BIT(4)
94 #define CAN_STM32FD_ILS_TFERR BIT(3)
95 #define CAN_STM32FD_ILS_SMSG BIT(2)
96 #define CAN_STM32FD_ILS_RXFIFO1 BIT(1)
97 #define CAN_STM32FD_ILS_RXFIFO0 BIT(0)
98
99 /* Global filter configuration register */
100 #define CAN_STM32FD_RXGFC 0x080
101 #define CAN_STM32FD_RXGFC_LSE GENMASK(27, 24)
102 #define CAN_STM32FD_RXGFC_LSS GENMASK(20, 16)
103 #define CAN_STM32FD_RXGFC_F0OM BIT(9)
104 #define CAN_STM32FD_RXGFC_F1OM BIT(8)
105 #define CAN_STM32FD_RXGFC_ANFS GENMASK(5, 4)
106 #define CAN_STM32FD_RXGFC_ANFE GENMASK(3, 2)
107 #define CAN_STM32FD_RXGFC_RRFS BIT(1)
108 #define CAN_STM32FD_RXGFC_RRFE BIT(0)
109
110 /* Extended ID AND Mask register */
111 #define CAN_STM32FD_XIDAM 0x084
112
113 /* High Priority Message Status register */
114 #define CAN_STM32FD_HPMS 0x088
115
116 /* Rx FIFO 0 Status register */
117 #define CAN_STM32FD_RXF0S 0x090
118
119 /* Rx FIFO 0 Acknowledge register */
120 #define CAN_STM32FD_RXF0A 0x094
121
122 /* Rx FIFO 1 Status register */
123 #define CAN_STM32FD_RXF1S 0x098
124
125 /* Rx FIFO 1 Acknowledge register */
126 #define CAN_STM32FD_RXF1A 0x09C
127
128 /* Tx Buffer Configuration register */
129 #define CAN_STM32FD_TXBC_TFQM BIT(24)
130
131 /* Tx Buffer Request Pending register */
132 #define CAN_STM32FD_TXBRP 0x0C8
133
134 /* Tx Buffer Add Request register */
135 #define CAN_STM32FD_TXBAR 0x0CC
136
137 /* Tx Buffer Cancellation Request register */
138 #define CAN_STM32FD_TXBCR 0x0D0
139
140 /* Tx Buffer Transmission Occurred register */
141 #define CAN_STM32FD_TXBTO 0x0D4
142
143 /* Tx Buffer Cancellation Finished register */
144 #define CAN_STM32FD_TXBCF 0x0D8
145
146 /* Tx Buffer Transmission Interrupt Enable register */
147 #define CAN_STM32FD_TXBTIE 0x0DC
148
149 /* Tx Buffer Cancellation Finished Interrupt Enable register */
150 #define CAN_STM32FD_TXBCIE 0x0E0
151
152 /* Tx Event FIFO Status register */
153 #define CAN_STM32FD_TXEFS 0x0E4
154
155 /* Tx Event FIFO Acknowledge register */
156 #define CAN_STM32FD_TXEFA 0x0E8
157
158 /* Register address indicating unsupported register */
159 #define CAN_STM32FD_REGISTER_UNSUPPORTED UINT16_MAX
160
161 /* This symbol takes the value 1 if one of the device instances */
162 /* is configured in dts with a domain clock */
163 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
164 #define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 1
165 #else
166 #define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 0
167 #endif
168
169 struct can_stm32fd_config {
170 mm_reg_t base;
171 mem_addr_t mram;
172 size_t pclk_len;
173 const struct stm32_pclken *pclken;
174 void (*config_irq)(void);
175 const struct pinctrl_dev_config *pcfg;
176 uint8_t clock_divider;
177 };
178
can_stm32fd_remap_reg(uint16_t reg)179 static inline uint16_t can_stm32fd_remap_reg(uint16_t reg)
180 {
181 uint16_t remap;
182
183 switch (reg) {
184 case CAN_MCAN_SIDFC:
185 __fallthrough;
186 case CAN_MCAN_XIDFC:
187 __fallthrough;
188 case CAN_MCAN_NDAT1:
189 __fallthrough;
190 case CAN_MCAN_NDAT2:
191 __fallthrough;
192 case CAN_MCAN_RXF0C:
193 __fallthrough;
194 case CAN_MCAN_RXBC:
195 __fallthrough;
196 case CAN_MCAN_RXF1C:
197 __fallthrough;
198 case CAN_MCAN_RXESC:
199 __fallthrough;
200 case CAN_MCAN_TXESC:
201 __fallthrough;
202 case CAN_MCAN_TXEFC:
203 __ASSERT_NO_MSG(false);
204 remap = CAN_STM32FD_REGISTER_UNSUPPORTED;
205 break;
206 case CAN_MCAN_XIDAM:
207 remap = CAN_STM32FD_XIDAM;
208 break;
209 case CAN_MCAN_RXF0S:
210 remap = CAN_STM32FD_RXF0S;
211 break;
212 case CAN_MCAN_RXF0A:
213 remap = CAN_STM32FD_RXF0A;
214 break;
215 case CAN_MCAN_RXF1S:
216 remap = CAN_STM32FD_RXF1S;
217 break;
218 case CAN_MCAN_RXF1A:
219 remap = CAN_STM32FD_RXF1A;
220 break;
221 case CAN_MCAN_TXBRP:
222 remap = CAN_STM32FD_TXBRP;
223 break;
224 case CAN_MCAN_TXBAR:
225 remap = CAN_STM32FD_TXBAR;
226 break;
227 case CAN_MCAN_TXBCR:
228 remap = CAN_STM32FD_TXBCR;
229 break;
230 case CAN_MCAN_TXBTO:
231 remap = CAN_STM32FD_TXBTO;
232 break;
233 case CAN_MCAN_TXBCF:
234 remap = CAN_STM32FD_TXBCF;
235 break;
236 case CAN_MCAN_TXBTIE:
237 remap = CAN_STM32FD_TXBTIE;
238 break;
239 case CAN_MCAN_TXBCIE:
240 remap = CAN_STM32FD_TXBCIE;
241 break;
242 case CAN_MCAN_TXEFS:
243 remap = CAN_STM32FD_TXEFS;
244 break;
245 case CAN_MCAN_TXEFA:
246 remap = CAN_STM32FD_TXEFA;
247 break;
248 default:
249 /* No register address remap needed */
250 remap = reg;
251 break;
252 };
253
254 return remap;
255 }
256
can_stm32fd_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)257 static int can_stm32fd_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
258 {
259 const struct can_mcan_config *mcan_config = dev->config;
260 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
261 uint16_t remap;
262 uint32_t bits;
263 int err;
264
265 remap = can_stm32fd_remap_reg(reg);
266 if (remap == CAN_STM32FD_REGISTER_UNSUPPORTED) {
267 return -ENOTSUP;
268 }
269
270 err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits);
271 if (err != 0) {
272 return err;
273 }
274
275 *val = 0U;
276
277 switch (reg) {
278 case CAN_MCAN_IR:
279 __fallthrough;
280 case CAN_MCAN_IE:
281 /* Remap IR/IE bits, ignoring unsupported bits */
282 /* Group 1 map bits 23-16 (stm32fd) to 29-22 (mcan) */
283 *val |= ((bits & GENMASK(23, 16)) << 6);
284
285 /* Group 2 map bits 15-11 (stm32fd) to 18-14 (mcan) */
286 *val |= ((bits & GENMASK(15, 11)) << 3);
287
288 /* Group 3 map bits 10-4 (stm32fd) to 12-6 (mcan) */
289 *val |= ((bits & GENMASK(10, 4)) << 2);
290
291 /* Group 4 map bits 3-1 (stm32fd) to 4-2 (mcan) */
292 *val |= ((bits & GENMASK(3, 1)) << 1);
293
294 /* Group 5 map bits 0 (mcan) to 0 (stm32fd) */
295 *val |= ((bits & GENMASK(0, 0)) << 0);
296 break;
297 case CAN_MCAN_ILS:
298 /* Only remap ILS groups used in can_mcan.c */
299 if ((bits & CAN_STM32FD_ILS_RXFIFO1) != 0U) {
300 *val |= CAN_MCAN_ILS_RF1LL | CAN_MCAN_ILS_RF1FL | CAN_MCAN_ILS_RF1NL;
301 }
302
303 if ((bits & CAN_STM32FD_ILS_RXFIFO0) != 0U) {
304 *val |= CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF0FL | CAN_MCAN_ILS_RF0NL;
305 }
306 break;
307 case CAN_MCAN_GFC:
308 /* Map fields from RXGFC excluding STM32 FDCAN LSS and LSE fields */
309 *val = bits & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |
310 CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE);
311 break;
312 default:
313 /* No field remap needed */
314 *val = bits;
315 break;
316 };
317
318 return 0;
319 }
320
can_stm32fd_write_reg(const struct device * dev,uint16_t reg,uint32_t val)321 static int can_stm32fd_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
322 {
323 const struct can_mcan_config *mcan_config = dev->config;
324 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
325 uint32_t bits = 0U;
326 uint16_t remap;
327
328 remap = can_stm32fd_remap_reg(reg);
329 if (remap == CAN_STM32FD_REGISTER_UNSUPPORTED) {
330 return -ENOTSUP;
331 }
332
333 switch (reg) {
334 case CAN_MCAN_IR:
335 __fallthrough;
336 case CAN_MCAN_IE:
337 /* Remap IR/IE bits, ignoring unsupported bits */
338 /* Group 1 map bits 29-22 (mcan) to 23-16 (stm32fd) */
339 bits |= ((val & GENMASK(29, 22)) >> 6);
340
341 /* Group 2 map bits 18-14 (mcan) to 15-11 (stm32fd) */
342 bits |= ((val & GENMASK(18, 14)) >> 3);
343
344 /* Group 3 map bits 12-6 (mcan) to 10-4 (stm32fd) */
345 bits |= ((val & GENMASK(12, 6)) >> 2);
346
347 /* Group 4 map bits 4-2 (mcan) to 3-1 (stm32fd) */
348 bits |= ((val & GENMASK(4, 2)) >> 1);
349
350 /* Group 5 map bits 0 (mcan) to 0 (stm32fd) */
351 bits |= ((val & GENMASK(0, 0)) >> 0);
352 break;
353 case CAN_MCAN_ILS:
354 /* Only remap ILS groups used in can_mcan.c */
355 if ((val & (CAN_MCAN_ILS_RF1LL | CAN_MCAN_ILS_RF1FL | CAN_MCAN_ILS_RF1NL)) != 0U) {
356 bits |= CAN_STM32FD_ILS_RXFIFO1;
357 }
358
359 if ((val & (CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF0FL | CAN_MCAN_ILS_RF0NL)) != 0U) {
360 bits |= CAN_STM32FD_ILS_RXFIFO0;
361 }
362 break;
363 case CAN_MCAN_GFC:
364 /* Map fields to RXGFC including STM32 FDCAN LSS and LSE fields */
365 bits |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |
366 FIELD_PREP(CAN_STM32FD_RXGFC_LSE, CONFIG_CAN_MAX_EXT_ID_FILTER);
367 bits |= val & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |
368 CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE);
369 break;
370 default:
371 /* No field remap needed */
372 bits = val;
373 break;
374 };
375
376 return can_mcan_sys_write_reg(stm32fd_config->base, remap, bits);
377 }
378
can_stm32fd_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)379 static int can_stm32fd_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
380 {
381 const struct can_mcan_config *mcan_config = dev->config;
382 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
383
384 return can_mcan_sys_read_mram(stm32fd_config->mram, offset, dst, len);
385 }
386
can_stm32fd_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)387 static int can_stm32fd_write_mram(const struct device *dev, uint16_t offset, const void *src,
388 size_t len)
389 {
390 const struct can_mcan_config *mcan_config = dev->config;
391 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
392
393 return can_mcan_sys_write_mram(stm32fd_config->mram, offset, src, len);
394 }
395
can_stm32fd_clear_mram(const struct device * dev,uint16_t offset,size_t len)396 static int can_stm32fd_clear_mram(const struct device *dev, uint16_t offset, size_t len)
397 {
398 const struct can_mcan_config *mcan_config = dev->config;
399 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
400
401 return can_mcan_sys_clear_mram(stm32fd_config->mram, offset, len);
402 }
403
can_stm32fd_get_core_clock(const struct device * dev,uint32_t * rate)404 static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
405 {
406 const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
407
408 ARG_UNUSED(dev);
409
410 if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
411 LOG_ERR("Can't read core clock");
412 return -EIO;
413 }
414
415 if (FDCAN_CONFIG->CKDIV == 0) {
416 *rate = rate_tmp;
417 } else {
418 *rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1);
419 }
420
421 return 0;
422 }
423
can_stm32fd_clock_enable(const struct device * dev)424 static int can_stm32fd_clock_enable(const struct device *dev)
425 {
426 int ret;
427 const struct can_mcan_config *mcan_cfg = dev->config;
428 const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
429 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
430
431 if (!device_is_ready(clk)) {
432 return -ENODEV;
433 }
434
435 if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {
436 ret = clock_control_configure(clk,
437 (clock_control_subsys_t)&stm32fd_cfg->pclken[1],
438 NULL);
439 if (ret < 0) {
440 LOG_ERR("Could not select can_stm32fd domain clock");
441 return ret;
442 }
443 }
444
445 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]);
446 if (ret < 0) {
447 return ret;
448 }
449
450 if (stm32fd_cfg->clock_divider != 0) {
451 can_mcan_enable_configuration_change(dev);
452 FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1;
453 }
454
455 return 0;
456 }
457
can_stm32fd_init(const struct device * dev)458 static int can_stm32fd_init(const struct device *dev)
459 {
460 const struct can_mcan_config *mcan_cfg = dev->config;
461 const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
462 uint32_t rxgfc;
463 int ret;
464
465 /* Configure dt provided device signals when available */
466 ret = pinctrl_apply_state(stm32fd_cfg->pcfg, PINCTRL_STATE_DEFAULT);
467 if (ret < 0) {
468 LOG_ERR("CAN pinctrl setup failed (%d)", ret);
469 return ret;
470 }
471
472 ret = can_stm32fd_clock_enable(dev);
473 if (ret < 0) {
474 LOG_ERR("Could not turn on CAN clock (%d)", ret);
475 return ret;
476 }
477
478 can_mcan_enable_configuration_change(dev);
479
480 /* Setup STM32 FDCAN Global Filter Configuration register */
481 ret = can_mcan_read_reg(dev, CAN_STM32FD_RXGFC, &rxgfc);
482 if (ret != 0) {
483 return ret;
484 }
485
486 rxgfc |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |
487 FIELD_PREP(CAN_STM32FD_RXGFC_LSE, CONFIG_CAN_MAX_EXT_ID_FILTER);
488
489 ret = can_mcan_write_reg(dev, CAN_STM32FD_RXGFC, rxgfc);
490 if (ret != 0) {
491 return ret;
492 }
493
494 /* Setup STM32 FDCAN Tx buffer configuration register */
495 ret = can_mcan_write_reg(dev, CAN_MCAN_TXBC, CAN_STM32FD_TXBC_TFQM);
496 if (ret != 0) {
497 return ret;
498 }
499
500 ret = can_mcan_init(dev);
501 if (ret != 0) {
502 return ret;
503 }
504
505 stm32fd_cfg->config_irq();
506
507 return ret;
508 }
509
510 static DEVICE_API(can, can_stm32fd_driver_api) = {
511 .get_capabilities = can_mcan_get_capabilities,
512 .start = can_mcan_start,
513 .stop = can_mcan_stop,
514 .set_mode = can_mcan_set_mode,
515 .set_timing = can_mcan_set_timing,
516 .send = can_mcan_send,
517 .add_rx_filter = can_mcan_add_rx_filter,
518 .remove_rx_filter = can_mcan_remove_rx_filter,
519 .get_state = can_mcan_get_state,
520 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
521 .recover = can_mcan_recover,
522 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
523 .get_core_clock = can_stm32fd_get_core_clock,
524 .get_max_filters = can_mcan_get_max_filters,
525 .set_state_change_callback = can_mcan_set_state_change_callback,
526 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
527 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
528 #ifdef CONFIG_CAN_FD_MODE
529 .set_timing_data = can_mcan_set_timing_data,
530 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
531 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
532 #endif /* CONFIG_CAN_FD_MODE */
533 };
534
535 static const struct can_mcan_ops can_stm32fd_ops = {
536 .read_reg = can_stm32fd_read_reg,
537 .write_reg = can_stm32fd_write_reg,
538 .read_mram = can_stm32fd_read_mram,
539 .write_mram = can_stm32fd_write_mram,
540 .clear_mram = can_stm32fd_clear_mram,
541 };
542
543 #define CAN_STM32FD_BUILD_ASSERT_MRAM_CFG(inst) \
544 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_STD_FILTER_ELEMENTS(inst) == 28, \
545 "Standard filter elements must be 28"); \
546 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_EXT_FILTER_ELEMENTS(inst) == 8, \
547 "Extended filter elements must be 8"); \
548 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_FIFO0_ELEMENTS(inst) == 3, \
549 "Rx FIFO 0 elements must be 3"); \
550 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_FIFO1_ELEMENTS(inst) == 3, \
551 "Rx FIFO 1 elements must be 3"); \
552 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_BUFFER_ELEMENTS(inst) == 0, \
553 "Rx Buffer elements must be 0"); \
554 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_ELEMENTS(inst) == 3, \
555 "Tx Event FIFO elements must be 3"); \
556 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst) == 3, \
557 "Tx Buffer elements must be 0");
558
559 #define CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
560 static void config_can_##inst##_irq(void) \
561 { \
562 LOG_DBG("Enable CAN" #inst " IRQ"); \
563 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, int0, irq), \
564 DT_INST_IRQ_BY_NAME(inst, int0, priority), \
565 can_mcan_line_0_isr, DEVICE_DT_INST_GET(inst), 0); \
566 irq_enable(DT_INST_IRQ_BY_NAME(inst, int0, irq)); \
567 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, int1, irq), \
568 DT_INST_IRQ_BY_NAME(inst, int1, priority), \
569 can_mcan_line_1_isr, DEVICE_DT_INST_GET(inst), 0); \
570 irq_enable(DT_INST_IRQ_BY_NAME(inst, int1, irq)); \
571 }
572
573 #define CAN_STM32FD_CFG_INST(inst) \
574 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(inst) <= \
575 CAN_MCAN_DT_INST_MRAM_SIZE(inst), \
576 "Insufficient Message RAM size to hold elements"); \
577 \
578 PINCTRL_DT_INST_DEFINE(inst); \
579 CAN_MCAN_CALLBACKS_DEFINE(can_stm32fd_cbs_##inst, \
580 CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst), \
581 CONFIG_CAN_MAX_STD_ID_FILTER, \
582 CONFIG_CAN_MAX_EXT_ID_FILTER); \
583 \
584 static const struct stm32_pclken can_stm32fd_pclken_##inst[] = \
585 STM32_DT_INST_CLOCKS(inst); \
586 \
587 static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
588 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
589 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(inst), \
590 .pclken = can_stm32fd_pclken_##inst, \
591 .pclk_len = DT_INST_NUM_CLOCKS(inst), \
592 .config_irq = config_can_##inst##_irq, \
593 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
594 .clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
595 }; \
596 \
597 static const struct can_mcan_config can_mcan_cfg_##inst = \
598 CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_stm32fd_cfg_##inst, \
599 &can_stm32fd_ops, \
600 &can_stm32fd_cbs_##inst);
601
602 #define CAN_STM32FD_DATA_INST(inst) \
603 static struct can_mcan_data can_mcan_data_##inst = \
604 CAN_MCAN_DATA_INITIALIZER(NULL);
605
606 #define CAN_STM32FD_DEVICE_INST(inst) \
607 CAN_DEVICE_DT_INST_DEFINE(inst, can_stm32fd_init, NULL, \
608 &can_mcan_data_##inst, &can_mcan_cfg_##inst, \
609 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
610 &can_stm32fd_driver_api);
611
612 #define CAN_STM32FD_INST(inst) \
613 CAN_STM32FD_BUILD_ASSERT_MRAM_CFG(inst) \
614 CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
615 CAN_STM32FD_CFG_INST(inst) \
616 CAN_STM32FD_DATA_INST(inst) \
617 CAN_STM32FD_DEVICE_INST(inst)
618
619 DT_INST_FOREACH_STATUS_OKAY(CAN_STM32FD_INST)
620
